Patents by Inventor Rohan S. Salvi

Rohan S. Salvi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for coding bits of data in parallel
    Publication number: 20040139383
    Abstract: A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. The memory receives and stores unpunctured ones of the MR code bits from the first encoder. The second encoder receives and codes N code bits in parallel in accordance with a second coding scheme to generate coded data. M and N can be any values (e.g., M≧8, N≧4). Each encoder can be a (e.g., a rate ½) convolutional encoder that implements a particular polynomial generator, and can be implemented with one or more look-up tables, a state machine, or some other design.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 15, 2004
    Inventors: Rohan S. Salvi, Michael A. Howard
  • Method and apparatus for coding bits of data in parallel
    Patent number: 6701482
    Abstract: A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. The memory receives and stores unpunctured ones of the MR code bits from the first encoder. The second encoder receives and codes N code bits in parallel in accordance with a second coding scheme to generate coded data. M and N can be any values (e.g., M≧8, N≧4). Each encoder can be a (e.g., a rate ½) convolutional encoder that implements a particular polynomial generator, and can be implemented with one or more look-up tables, a state machine, or some other design.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: March 2, 2004
    Assignee: Qualcomm Incorporated
    Inventors: Rohan S. Salvi, Michael A. Howard
  • Method and apparatus for coding bits of data in parallel
    Publication number: 20030101401
    Abstract: A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. The memory receives and stores unpunctured ones of the MR code bits from the first encoder. The second encoder receives and codes N code bits in parallel in accordance with a second coding scheme to generate coded data. M and N can be any values (e.g., M≧8, N≧4). Each encoder can be a (e.g., a rate ½) convolutional encoder that implements a particular polynomial generator, and can be implemented with one or more look-up tables, a state machine, or some other design.
    Type: Application
    Filed: September 20, 2001
    Publication date: May 29, 2003
    Inventors: Rohan S. Salvi, Michael A. Howard