Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: A cache comprises a memory including a plurality of entries and a circuit. Each entry of the plurality of entries is configured to store a cache block. The circuit is configured to select a first entry of the plurality of entries to store a first cache block. In one implementation, the first cache block corresponds to a first transaction initiated by a first agent, wherein the first entry is selected from a first subset of the plurality of entries indicated as selectable for the first agent. In another implementation, the circuit is configured to select the first entry of the plurality of entries in response to whether the first cache block is a remote cache block or a local cache block. In other implementations, the circuit may be configured to handle a combination of the above.

Abstract: A cache comprises a memory including a plurality of entries and a circuit. Each entry of the plurality of entries is configured to store a cache block. The circuit is configured to select a first entry of the plurality of entries to store a first cache block. In one implementation, the first cache block corresponds to a first transaction initiated by a first agent, wherein the first entry is selected from a first subset of the plurality of entries indicated as selectable for the first agent. In another implementation, the circuit is configured to select the first entry of the plurality of entries in response to whether the first cache block is a remote cache block or a local cache block. In other implementations, the circuit may be configured to handle a combination of the above.