Abstract: A voltage supervisor includes a first transistor coupled between a first supply voltage and a second supply voltage. The voltage supervisor includes a second transistor coupled between the first supply voltage and the second supply voltage. The voltage supervisor is configured to provide a first current proportional to a difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is also configured to provide a second current proportional to a difference in the first supply voltage and the difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is configured to compare the first current to the second current to determine a voltage value that changes a state responsive to the first supply voltage crossing a threshold.

Abstract: A voltage supervisor includes a first transistor coupled between a first supply voltage and a second supply voltage. The voltage supervisor includes a second transistor coupled between the first supply voltage and the second supply voltage. The voltage supervisor is configured to provide a first current proportional to a difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is also configured to provide a second current proportional to a difference in the first supply voltage and the difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is configured to compare the first current to the second current to determine a voltage value that changes a state responsive to the first supply voltage crossing a threshold.

Abstract: Described embodiments include a voltage regulator circuit comprising an output voltage terminal configured to be coupled to a load that draws a load current, first and second amplifiers, and first, second, third, fourth and fifth transistors. The embodiment also includes a dynamic R-C network coupled between the third amplifier input and the seventh transistor current terminal, wherein the dynamic R-C network includes capacitors and MOS-based resistors, a third amplifier having a fourth amplifier input and a third amplifier output, wherein the fourth amplifier input is coupled to the output voltage terminal, and a capacitor that is coupled between the output voltage terminal and the fourth amplifier input.

Abstract: One example includes a circuit. The circuit includes a first transistor having a first control terminal, a first current terminal, and a second current terminal. The first control terminal can be a first input to the circuit. The circuit also includes a second transistor having a second control terminal, a first current terminal, and a second current terminal. The second control terminal can be a second input to the circuit. The circuit also includes an adaptive bias current source coupled to the second current terminal of the respective first and second transistors. The circuit further includes a voltage offset generator coupled in parallel with the second transistor.

Abstract: Described embodiments include a voltage regulator circuit comprising an output voltage terminal configured to be coupled to a load that draws a load current, first and second amplifiers, and first, second, third, fourth and fifth transistors. The embodiment also includes a dynamic R-C network coupled between the third amplifier input and the seventh transistor current terminal, wherein the dynamic R-C network includes capacitors and MOS-based resistors, a third amplifier having a fourth amplifier input and a third amplifier output, wherein the fourth amplifier input is coupled to the output voltage terminal, and a capacitor that is coupled between the output voltage terminal and the fourth amplifier input.

Abstract: Described embodiments include a voltage regulator circuit comprising an output voltage terminal configured to be coupled to a load that draws a load current, first and second amplifiers, and first, second, third, fourth and fifth transistors. The embodiment also includes a dynamic R-C network coupled between the third amplifier input and the seventh transistor current terminal, wherein the dynamic R-C network includes capacitors and MOS-based resistors, a third amplifier having a fourth amplifier input and a third amplifier output, wherein the fourth amplifier input is coupled to the output voltage terminal, and a capacitor that is coupled between the output voltage terminal and the fourth amplifier input.

Abstract: A circuit includes a reference voltage generator circuit and a regulation loop circuit having an output voltage terminal. The regulator circuit further includes a fault detection circuit having a first input terminal coupled to the output voltage regulator terminal of the regulation loop circuit. The fault detection circuit asserts, on an output terminal of the fault detection circuit, a fault flag signal responsive to a voltage on the first input terminal falling below a first threshold. A programmable filter is coupled between the reference voltage generator circuit and the regulation loop circuit and is coupled to the fault detection circuit. The programmable filter has a programmable time constant. The programmable filter responds to an assertion of the fault flag signal by decreasing the time constant.

Abstract: Described embodiments include a voltage regulator circuit comprising an output voltage terminal configured to be coupled to a load that draws a load current, first and second amplifiers, and first, second, third, fourth and fifth transistors. The embodiment also includes a dynamic R-C network coupled between the third amplifier input and the seventh transistor current terminal, wherein the dynamic R-C network includes capacitors and MOS-based resistors, a third amplifier having a fourth amplifier input and a third amplifier output, wherein the fourth amplifier input is coupled to the output voltage terminal, and a capacitor that is coupled between the output voltage terminal and the fourth amplifier input.

Abstract: A circuit includes first and second transistors, an adaptive bias current source circuit, and an adaptive resistance circuit. The first transistor has a control terminal and first and second current terminals. The control terminal of the first transistor being a first input to the circuit. The second transistor has a control terminal and first and second current terminals, and the control terminal of the second transistor is a second input to the circuit. The first and second inputs are differential inputs to the circuit. The adaptive bias current source circuit is coupled to the second current terminal of the first transistor. The adaptive resistance circuit is coupled between the second current terminal of the second transistor and the adaptive bias current source circuit.

Abstract: A voltage supervisor includes a first transistor coupled between a first supply voltage and a second supply voltage. The voltage supervisor includes a second transistor coupled between the first supply voltage and the second supply voltage. The voltage supervisor is configured to provide a first current proportional to a difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is also configured to provide a second current proportional to a difference in the first supply voltage and the difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is configured to compare the first current to the second current to determine a voltage value that changes a state responsive to the first supply voltage crossing a threshold.

Abstract: A circuit includes first and second transistors, an adaptive bias current source circuit, and an adaptive resistance circuit. The first transistor has a control terminal and first and second current terminals. The control terminal of the first transistor being a first input to the circuit. The second transistor has a control terminal and first and second current terminals, and the control terminal of the second transistor is a second input to the circuit. The first and second inputs are differential inputs to the circuit. The adaptive bias current source circuit is coupled to the second current terminal of the first transistor. The adaptive resistance circuit is coupled between the second current terminal of the second transistor and the adaptive bias current source circuit.

Abstract: A circuit includes a reference voltage generator circuit and a regulation loop circuit having an output voltage terminal. The regulator circuit further includes a fault detection circuit having a first input terminal coupled to the output voltage regulator terminal of the regulation loop circuit. The fault detection circuit asserts, on an output terminal of the fault detection circuit, a fault flag signal responsive to a voltage on the first input terminal falling below a first threshold. A programmable filter is coupled between the reference voltage generator circuit and the regulation loop circuit and is coupled to the fault detection circuit. The programmable filter has a programmable time constant. The programmable filter responds to an assertion of the fault flag signal by decreasing the time constant.

Abstract: A circuit includes a first power transistor including a first control input and first and second current terminals. The circuit includes a second power transistor including a second control input and third and fourth current terminals. Third current terminal couples to the first current terminal, and the fourth current terminal couples to the second current terminal at an output node. An error amplifier generates an error signal based on a difference between a reference voltage and an output voltage on the output node. An adaptive buffer couples to an output of the error amplifier and couples to the first and second control inputs. The adaptive buffer causes the first power transistor to be on through a range of output current and to cause the second power transistor to be on through some, but not all, of the range of output current.

Abstract: A voltage regulator circuit comprises: a pass transistor comprising a gate, a source, and a drain; an error amplifier comprising an output port coupled to the gate of the pass transistor, a first input port, and a second input port; a feedback circuit coupled to the drain of the pass transistor, and coupled to the first input port of the error amplifier to provide a feedback voltage at the first input port of the error amplifier; a sink transistor comprising a gate, a source, and a drain coupled to the drain of the pass transistor; a sink gate voltage circuit coupled to the gate of the sink transistor to provide a gate voltage at the gate of the sink transistor; and a pass gate sensing circuit coupled to the output port of the error amplifier to provide current to the sink gate voltage circuit.

Abstract: A voltage regulator circuit comprises: a pass transistor comprising a gate, a source, and a drain; an error amplifier comprising an output port coupled to the gate of the pass transistor, a first input port, and a second input port; a feedback circuit coupled to the drain of the pass transistor, and coupled to the first input port of the error amplifier to provide a feedback voltage at the first input port of the error amplifier; a sink transistor comprising a gate, a source, and a drain coupled to the drain of the pass transistor; a sink gate voltage circuit coupled to the gate of the sink transistor to provide a gate voltage at the gate of the sink transistor; and a pass gate sensing circuit coupled to the output port of the error amplifier to provide current to the sink gate voltage circuit.