Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

Abstract: A first node can be selected as a target node, and a second node can be selected as a control to determine a performance limit associated with providing a service. A request for the service can be determined to be routed to the first node. A first indication of a first performance measurement associated with processing a first load by the first node can be received. A second indication of a second performance measurement associated with processing a second load by the second node can be received. A performance error of the first node can be determined based on the first performance measurement and the second performance measurement. The performance limit can be determined based on the performance error, and an action can be triggered based on the performance limit.