Patents by Inventor Rohith MS

Rohith MS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and framework to dynamically split a testbench into concurrent simulatable multi-processes and attachment to parallel processes of an accelerated platform
    Patent number: 10719644
    Abstract: The independent claims of this patent signify a concise description of embodiments. Each component of a testbench configured to test a DUT is associated at compile time with a different hardware transactor. The testbench is partitioned at compile time into a plurality of independent partitioned testbenches, where each independent partitioned testbench comprises at least one component of the testbench. At run time, each of the plurality of partitioned testbenches is simulated in parallel. The simulating of a partitioned testbench includes execution of its at least one component on its at least one associated hardware transactor using the hardware emulation system. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 21, 2020
    Assignee: Synopsys, Inc.
    Inventors: Amit Sharma, Rohith MS, Prashanth Srinivasa
  • METHOD AND FRAMEWORK TO DYNAMICALLY SPLIT A TESTBENCH INTO CONCURRENT SIMULATABLE MULTI-PROCESSES AND ATTACHMENT TO PARALLEL PROCESSES OF AN ACCELERATED PLATFORM
    Publication number: 20190005177
    Abstract: The independent claims of this patent signify a concise description of embodiments. Each component of a testbench configured to test a DUT is associated at compile time with a different hardware transactor. The testbench is partitioned at compile time into a plurality of independent partitioned testbenches, where each independent partitioned testbench comprises at least one component of the testbench. At run time, each of the plurality of partitioned testbenches is simulated in parallel. The simulating of a partitioned testbench includes execution of its at least one component on its at least one associated hardware transactor using the hardware emulation system. This Abstract is not intended to limit the scope of the claims.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 3, 2019
    Inventors: Amit SHARMA, Rohith MS, Prashanth SRINIVASA