Patents by Inventor Rohith SOMAN

Rohith SOMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked buffer in transistors
    Patent number: 11973137
    Abstract: The present subject matter provides a High Mobility Electron Transistor (HEMT) comprising: a substrate, a nucleation layer provided on the substrate, a channel layer, and a buffer layer formed between the nucleation layer and the channel layer. The buffer layer comprises a vertical stack of p-n junctions. Each p-n junction of the vertical stack of p-n junctions comprises an n-type layer provided on a p-type layer. The n-type layer and the p-type layer are parallel to the substrate.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 30, 2024
    Assignee: Indian Institute of Science
    Inventors: Srinivasan Raghavan, Navakanta Bhat, Rohith Soman
  • High electron mobility transistor (HEMT) with RESURF junction
    Patent number: 11522078
    Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 6, 2022
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Rohith Soman, Ankit Soni, Mayank Shrivastava, Srinivasan Raghavan, Navakant Bhat
  • STACKED BUFFER IN TRANSISTORS
    Publication number: 20220020871
    Abstract: The present subject matter provides a High Mobility Electron Transistor (HEMT) comprising: a substrate, a nucleation layer provided on the substrate, a channel layer, and a buffer layer formed between the nucleation layer and the channel layer. The buffer layer comprises a vertical stack of p-n junctions. Each p-n junction of the vertical stack of p-n junctions comprises an n-type layer provided on a p-type layer. The n-type layer and the p-type layer are parallel to the substrate.
    Type: Application
    Filed: December 5, 2019
    Publication date: January 20, 2022
    Inventors: Srinivasan RAGHAVAN, Navakanta BHAT, Rohith SOMAN
  • HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION
    Publication number: 20200227543
    Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.
    Type: Application
    Filed: July 6, 2018
    Publication date: July 16, 2020
    Inventors: Rohith SOMAN, Ankit SONI, Mayank SHRIVASTAVA, Srinivasan RAGHAVAN, Navakant BHAT