Abstract: The invention relates to new quinoline, isoquinoline and phthalazine derivatives as antagonists of the gonadotropin-releasing hormone.

Abstract: The invention relates to new quinoline, isoquinoline and phthalazine derivatives as antagonists of the gonadotropin-releasing hormone.

Abstract: The present invention relates to a compound of formula (I): where R1-R6, W, X, and Y are defined herein, a composition includung the compound of formula (I), and a method for, e.g., male birth control, including administering an effective amount of a compound of formula (I) to a patient in need thereof.

Abstract: A bus interface device for a data processing system in which 2M units are interconnected and exchange information bits over a bus comprising at least M lines.The device comprises a receiving circuit associated with each respective line (D0-D7) of the bus and including two flip-flops 40 and 41 that assume the voltage level on the input line at the up-going and down-going transitions of a clock signal (CLK1) and are restored at the down-going and up-going transitions of that signal. When the bits received over the bus are encoded in the NRZ code, using a bit period equal to half a period of the clock signal, OR circuit 47 provides at its output the resynchronized train of input bits received over D0-D7.The 2M units are divided into two groups, with the units in each group requesting access to the bus during either phase of a second clock signal (CLK2). When the bus is free, flip-flops 48 and 49 provide an indication of the requests for access to the bus made by the associated units.

Abstract: In the modem based data transmission system the transmitting section provides a bit from each terminal (DTE) to be stored into a transmission buffer register (BX) under the control of an external clock signal derived from a modem internal transmission clock signal. The contents of the transmission buffer register is transferred into a transmission shift register and then transferred toward the modem through a formatting logic circuit wherein so-called stuffing bits and synchronization or flag characters are being inserted. Opposite operations are performed in the receiving section of the data transmission system.

Abstract: A specialized processor capable of computing a sum of products S=.SIGMA..+-.Pi where every product Pi is the product of two n-bit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand, where j=.sqroot.-1. The processor includes an instruction storage, means for decoding instructions read out of said storage and for controlling the operation of the processor, a data storage, and a multiplication and accumulation unit which has two multiplier-accumulator devices and several buffers for storing the operands Ai, Bi, Ci and Di sequentially read out of data storage. The real part Ai and the imaginary part Bi of the multiplier are respectively applied to the Multiplier inputs of the multiplier-accumulator devices and the real part Ci of the multiplicand is applied to the Multiplicand inputs of the multiplier-accumulator devices, which simultaneously compute the products Ai Ci and Bi Ci.