Abstract: The invention relates to a method for the computer-assisted analysis of buggy source code in a hardware description language describing the structure and the operation of an integrated circuit. A correction model is provided, which includes a hierarchical structure of nodes arranged in a plurality of hierarchical levels, the nodes being transformation instructions, wherein a transformation instruction describes a group of transformations which are applied to at least one type of a source code section and thereby change the source code section and wherein a transformation instruction, which is a child node of another transformation instruction, constitutes a subset of the group of transformations of the other transformation instruction. Those transformation instructions, which change the source code in such a manner that the changed source code leads to a correct output of the integrated circuit, are determined and output together with the associated source code sections as corrections.

Abstract: The invention creates a technology for validating simulation results. The quickly growing number of components in modern complex systems often necessitates the introduction of abstractions, that render said systems manageable. However the abstractions, which often are based simplified assumptions, may impair the simulation results. The automatic post-processing method according to the invention safeguards the validity of the result. In most cases this can be reached, without restoring the complete description, which generally is too complex. The method, which is described for the validation of calculated counter-examples in an equivalence comparison of digital circuits can be used in all other applications, that allow for an analagous formalization of the abstraction step.