Abstract: Embodiments herein relate to a universal component interconnect express (UCIe) link that includes a mainband and a sideband. One or more pieces of logic may identify a data that is to be transmitted on the sideband. The logic may then identify, based on factors such as a characteristic of the data or a characteristic of the link, whether to transmit the data on the mainband. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to performing testing of a device while a system is operational. A device may include computing circuitry and host connectivity registers. Host connectivity registers contain configuration and memory mapping data programmed by system software upon power up of the device and computing system. The data contained in host connectivity registers should be always maintained while the computing system is operational. Scan test circuitry may be implemented, providing the ability to test the device while the system is operational. Preservation circuitry preserves or maintains the data stored in host connectivity registers allowing in-operation testing of the device, ensuring the device the ability to return to full operation at the end of in-operation testing without requiring system software to reprogram the host connectivity registers.

Abstract: Time to read the data registers in a remote Test Access Port (TAP) in a subsystem in a System-on-Chip (SoC) is reduced by reading multiple data registers in remote Test Access Ports in parallel. A Test Access Port Bridge provides access to multiple same width data registers in parallel. The same width data registers can be for the same function or different functions. The subsystems with a remote Test Access Port in the SoC can include Peripheral Component Interconnect Express (PCIe), Voltage Droop Monitors (VDMs), In-Die Variation (IDV) Monitor fub-lets, Temperature Sensors, Performance Monitors and telemetry subsystems.

Abstract: Embodiments herein relate to a logic configured to: identify, based on a header of a first packet, that the first packet is related to a first debug process of a component to which the logic is communicatively coupled, wherein the first debug process is performed by a first DTS; identify, based on a header of a second packet, that the second packet is related to a second debug process of the component, wherein the second debug process is performed by a second DTS; route, based on the identification that the first packet is related to the first debug process, the first packet between the component and the DTS; and route, based on the identification that the second packet is related to the second debug process, the second packet between the component and the DTS. Other embodiments may be described and/or claimed.

Abstract: In one embodiment, a processor includes: a first plurality of intellectual property (IP) circuits to execute operations; and a second plurality of integrated voltage regulators, where the second plurality of integrated voltage regulators are oversubscribed with respect to the first plurality of IP circuits. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes: a first plurality of intellectual property (IP) circuits to execute operations; and a second plurality of integrated voltage regulators, where the second plurality of integrated voltage regulators are oversubscribed with respect to the first plurality of IP circuits. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to techniques for extending I3C capability across multiple platforms and devices over a Universal Serial Bus (USB) type C (USB-C) connection are described. In one embodiment, a first device is coupled to a second device via a first interface and a second interface. The first interface is to communicate low-speed messages and data between the first device and the second device and the second interface is to communicate high-speed data between the first device and the second device. The first device comprises an extension controller to communicatively couple one or more target devices of the first device to one or more target devices of the second device via the first interface. Other embodiments are also claimed and disclosed.

Abstract: A debug test system is provided. The debug test system includes one or more interfaces configured to communicate with a target system and processing circuitry configured to control the one or more interfaces. Further, the processing circuitry is configured to receive information about an operation state of the target system from the target system and to generate control information for the target system to adjust a debug session on the target system. The processing circuitry is further configured to transmit the control information to the target system.

Abstract: Technologies for efficiently providing reliable compute operations for mission critical applications include a reliability management system. The reliability management system includes circuitry configured to obtain conclusion data indicative of a conclusion made by each of two or fewer compute devices of a host system. The conclusion data from each compute device pertains to the same operation. Additionally, the circuitry is configured to identify whether an error has occurred in the operation of each compute device, determine, in response to a determination that an error has occurred, a severity of the error, and cause the host system to perform a responsive action as a function of the determined severity of the error.

Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.

Abstract: One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.

Abstract: In one embodiment, an apparatus includes: a first hardware circuit to execute operations and a trace hardware circuit coupled to the first hardware circuit. At least one virtualization environment to be instantiated by a virtualization environment controller is to execute on the first hardware circuit. The virtualization environment controller may receive from a first virtualization environment a first trace message and a first platform description identifier to identify the first virtualization environment, remap the first platform description identifier to a second platform description identifier and send the first trace message and the second platform description identifier to the trace hardware circuit. In turn, the trace hardware circuit may send the first trace message and the second platform description identifier to a debug and test system. Other embodiments are described and claimed.

Abstract: Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.

Abstract: In one embodiment, a processor includes: a first plurality of intellectual property (IP) circuits to execute operations; and a second plurality of integrated voltage regulators, where the second plurality of integrated voltage regulators are oversubscribed with respect to the first plurality of IP circuits. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.

Abstract: Technologies for efficiently providing reliable compute operations for mission critical applications include a reliability management system. The reliability management system includes circuitry configured to obtain conclusion data indicative of a conclusion made by each of two or fewer compute devices of a host system. The conclusion data from each compute device pertains to the same operation. Additionally, the circuitry is configured to identify whether an error has occurred in the operation of each compute device, determine, in response to a determination that an error has occurred, a severity of the error, and cause the host system to perform a responsive action as a function of the determined severity of the error.

Abstract: Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.

Abstract: One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.