Patents by Inventor Rolf-Peter Vollertsen

Rolf-Peter Vollertsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9419619
    Abstract: A chip includes a logic circuit which has a plurality of transistors and is configured to carry out a logical data processing function, the transistors being operated in a first direction when carrying out the data processing function, and a readout circuit which is configured to control the logic circuit in such a manner that the transistors are operated in a second direction opposite the first direction and is configured to determine an identification of the logic circuit on the basis of an output from the logic circuit when operating the transistors in the second direction.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Georg Tempel, Rolf-Peter Vollertsen
  • Publication number: 20160094229
    Abstract: A chip includes a logic circuit which has a plurality of transistors and is configured to carry out a logical data processing function, the transistors being operated in a first direction when carrying out the data processing function, and a readout circuit which is configured to control the logic circuit in such a manner that the transistors are operated in a second direction opposite the first direction and is configured to determine an identification of the logic circuit on the basis of an output from the logic circuit when operating the transistors in the second direction.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 31, 2016
    Inventors: Georg TEMPEL, Rolf-Peter VOLLERTSEN
  • Patent number: 9086328
    Abstract: An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: July 21, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Rolf-Peter Vollertsen
  • Publication number: 20120276675
    Abstract: An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress.
    Type: Application
    Filed: July 9, 2012
    Publication date: November 1, 2012
    Inventor: Rolf-Peter Vollertsen
  • Patent number: 8215830
    Abstract: An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: July 10, 2012
    Assignee: Infineon Technologies AG
    Inventor: Rolf-Peter Vollertsen
  • Publication number: 20100322285
    Abstract: An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress.
    Type: Application
    Filed: August 26, 2010
    Publication date: December 23, 2010
    Inventor: Rolf-Peter Vollertsen
  • Patent number: 7798703
    Abstract: An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: September 21, 2010
    Assignee: Infineon Technologies AG
    Inventor: Rolf-Peter Vollertsen
  • Publication number: 20100019398
    Abstract: A semiconductor circuit element for reducing undesirable charging effects for a connection element of test structures for semiconductor circuits is disclosed. A surface of a semiconductor circuit element has interconnect structures that are electrically insulated from the remainder of the surface of the semiconductor circuit element, where exclusively the interconnect structures are connected to semiconductor circuit elements arranged downstream.
    Type: Application
    Filed: October 7, 2009
    Publication date: January 28, 2010
    Inventor: Rolf-Peter Vollertsen
  • Patent number: 7646104
    Abstract: A semiconductor circuit element for reducing undesirable charging effects for a connection element of test structures for semiconductor circuits is disclosed. A surface of a semiconductor circuit element has interconnect structures that are electrically insulated from the remainder of the surface of the semiconductor circuit element, where exclusively the interconnect structures are connected to semiconductor circuit elements arranged downstream.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: January 12, 2010
    Assignee: Infineon Technologies A.G.
    Inventor: Rolf-Peter Vollertsen
  • Publication number: 20080279252
    Abstract: An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 13, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Rolf-Peter Vollertsen
  • Publication number: 20060097253
    Abstract: A semiconductor circuit element for reducing undesirable charging effects for a connection element of test structures for semiconductor circuits is disclosed. A surface of a semiconductor circuit element has interconnect structures that are electrically insulated from the remainder of the surface of the semiconductor circuit element, where exclusively the interconnect structures are connected to semiconductor circuit elements arranged downstream.
    Type: Application
    Filed: December 20, 2005
    Publication date: May 11, 2006
    Inventor: Rolf-Peter Vollertsen
  • Patent number: 6465370
    Abstract: A method for reducing a capacitance formed on a silicon substrate includes the step of introducing hydrogen atoms into a portion of said surface to increase the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric material and hence reducing said capacitance. The method includes the step of forming the silicon dioxide layer with a thickness greater than two nanometers. The step of introducing hydrogen includes forming hydrogen atoms in the surface with concentrations of 1017 atoms per cubic centimeter, or greater. In one embodiment the hydrogen atoms are introduced by baking in hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr. A trench capacitor DRAM cell is provided wherein the hydrogen provides a passivation layer to increase the effective capacitance around a collar region and thereby reduce unwanted transistor action.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: October 15, 2002
    Assignee: Infineon Technologies AG
    Inventors: Martin Schrems, Rolf-Peter Vollertsen, Joachim Hoepfner
  • Publication number: 20020025622
    Abstract: A method for reducing a capacitance formed on a silicon substrate. The capacitance has, as a dielectric material thereof, a silicon dioxide layer on a surface of the silicon substrate. The method includes the step of introducing hydrogen atoms into a portion of said surface to increase the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric material and hence reducing said capacitance. The method including the step of forming the silicon dioxide layer with a thickness greater than two nanometers. The step of introducing hydrogen comprises the step of forming hydrogen atoms in the surface with concentrations of 1017 atoms per cubic centimeter, or greater. In one embodiment the hydrogen atoms are formed by baking in hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr.
    Type: Application
    Filed: February 4, 2000
    Publication date: February 28, 2002
    Inventors: Martin Schrems, Rolf-Peter Vollertsen, Joachim Hoepfner