Abstract: An electronic device includes a substrate plate with a traversing passage. An electronic component, mounted to the substrate plate, includes an integrated circuit chip with an optical sensor and an opaque protective plate mounted above the sensor. The electronic component is mounted with the chip facing the substrate plate such that the protective plate is engaged with the traversing passage. Electrical connection elements extend between the chip and the substrate plate. An internal block of encapsulation material extends into the traversing passage of the substrate plate between the chip and the substrate plate so as to embed the electrical connection elements.

Abstract: An electronic package includes a substrate wafer having front and rear faces. An emitting integrated circuit chip is mounted to the front face of the substrate wafer and includes a light radiation optical emitter. A receiving integrated circuit chip is also mounted to the front face of the substrate wafer and includes at least one light radiation optical sensor. A transparent encapsulant extends above the optical sensor and the optical emitter. An opaque encapsulant encapsulates the transparent encapsulant. The opaque encapsulant has a front window situated above the optical emitter and which is offset laterally relative to the optical sensor. The transparent encapsulant accordingly has an uncovered front face situated above the optical emitter and offset laterally relative to the optical sensor. The opaque encapsulant may include an additional front window. The receiving integrated circuit chip further includes a second optical sensor situated opposite the additional front window.

Abstract: An electronic package includes a substrate wafer having front and rear faces and a through passage having a front window and a blind cavity communicating laterally with the front window. A receiving integrated circuit chip is mounted on the rear face and includes an optical sensor situated opposite the blind cavity. A transparent encapsulant extends above the optical sensor and at least partially fills the through passage. An emitting integrated circuit chip, embedded in the transparent encapsulant, includes an optical emitter of luminous radiation. The emitting integrated circuit chip may be mounted to the front face or within the through passage to the receiving integrated circuit chip. The substrate wafer may further include a second through passage. The receiving integrated circuit chip further includes a second optical sensor situated opposite the second through passage. A cover plate is mounted to the front face at the second through passage.

Abstract: An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip.

Abstract: An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer.

Abstract: An electronic device is formed by a stack of an integrated circuit chip and an optical plate. The integrated circuit chip includes integrated circuits (such as optical circuits) formed on or in a semiconductor substrate plate. The optical integrated circuits may form an optical sensor. An electrical connection network is provided on the top side of the semiconductor substrate plate. Electrical connection lugs, which are connected to the electrical connection network through electrical connection vias, are mounted on the back side of the semiconductor substrate plate. The vias are through silicon vias situated at a distance from the periphery of the semiconductor substrate plate. The optical plate is configured to allow light radiation to pass to the optical integrated circuits.

Abstract: A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

Abstract: An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer.

Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.

Abstract: A first component includes a slice formed from an integrated circuit chip having a front face and a rear face. An encapsulation block encapsulates the integrated circuit chip such that front and rear faces of the chip and front and rear faces of the encapsulation block are co-planar to form front and rear faces of the slice. Front and rear electrical connection networks are provided on the front and rear faces, respectively, with the electrical connection networks linked by electrical connection vias passing through the encapsulation block. A thermal transfer layer at least partially covers the rear face. A second component may be behind and at a distance from the first component. Connection elements interposed between the first component and the second component include both thermal connection elements in contact with the thermal transfer layer and electrical connection elements interconnecting the first and second components.

Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

Abstract: A semiconductor package includes a transmissive support plate and includes at least one elongate hole. An integrated circuit semiconductor device is mounted on a rear face of the support plate. The semiconductor device includes first and second optical elements oriented towards the rear face of the support plate, where the first and second optical elements are placed on either side of the elongate hole. An encapsulation material made of an opaque material encapsulates the semiconductor device and fills the elongate hole so as to form an optical insulation partition between the first and second optical elements. A cavity is left, however, between each optical element and a rear face of the support plate.

Abstract: A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.

Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

Abstract: A surface-mounted electronic component including balls bonded to its front surface and, on the front surface, a protective resin layer having a thickness smaller than the ball height, wherein grooves extend in the resin layer between balls of the chip.

Abstract: A package includes a substrate with an attached emitting IC chip and receiving IC chip. The emitting IC chip includes an optical emitter, and the receiving IC chip includes a main optical sensor and a secondary optical sensor. A case is provided with a bottom portion and a peripheral wall portion to cover the IC chips, wherein the edge of the peripheral wall portion is mounted to the substrate. The bottom portion of the case includes a main opening above the main optical sensor and a secondary opening above the optical emitter. An opaque material is interposed between the case and the receiving IC chip to isolate the main optical sensor from the secondary optical sensor and delimiting a chamber containing the secondary optical sensor and the optical emitter. The chamber is optically isolated from the main optical sensor and main opening, and may be filled with a transparent material.

Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

Abstract: A manufacturing process includes forming a reconstituted wafer, including embedding semiconductor dice in a molding compound layer and forming through-wafer vias in the layer. A fan-out redistribution layer is formed on a front side of the wafer, with electrical traces interconnecting the dice, through-wafer vias, and contact pads positioned on the redistribution layer. Solder balls are positioned on the contact pads and a molding compound layer is formed on the redistribution layer, reinforcing the solder balls. A second fan-out redistribution layer is formed on a back side of the wafer, with electrical traces interconnecting back ends of the through-wafer vias and contact pads positioned on a back face of the second redistribution layer. Flip-chips and/or surface-mounted devices are coupled to the contact pads of the second redistribution layer and encapsulated in an underfill layer formed on the back face of the second redistribution layer.

Abstract: An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip.