Abstract: A service processor communication method includes establishing a communication channel between a service processor and a central processor in a computing system, wherein communication on the communication channel is independent of processing by the central processor, monitoring an operating system that is under control by the central processor, defining a source designator associated with state information of the operating system, and that is passed via the communication channel between the service processor and the central processor; and announcing the state information to a resource external to the computing system.

Abstract: A service processor communication method includes establishing a communication channel between a service processor and a central processor in a computing system, wherein communication on the communication channel is independent of processing by the central processor, monitoring an operating system that is under control by the central processor, defining a source designator associated with state information of the operating system, and that is passed via the communication channel between the service processor and the central processor; and announcing the state information to a resource external to the computing system.

Abstract: In a computing system having swappable and non-swappable address spaces, wherein the computing system includes an operating system that includes a Real Storage Manager (RSM), a Systems Resource Manager (SRM) and a Region Control Task (RCT), a method for recovering swappable fixed non-preferred memory is provided which includes receiving a request from the operating system to configure an area of real memory to create an intercepted swappable address space, wherein the intercepted swappable address space includes a flagged fixed frame element identified for configuration, examining the intercepted swappable address space so as to determine if the intercepted swappable address space will remain swappable, requesting the SRM to coordinate the swapping process, quiescing the intercepted address space, generating a first return code responsive to the intercepted swappable address space remaining swappable, communicating the first return code to the RCT so as to cause the RCT to respond to the first return code, in

Abstract: A method for using ancillary processors and memory to speed critical data capture includes building a list memory address ranges associated with a secondary partition. The memory address ranges are located in central storage memory and contain the data to be captured. The method also includes reading the data from the memory address ranges and writing the data to a portion of memory reserved by a first partition as a capture pool. The capture pool is also located in central storage memory and is not accessible by the secondary partition. The invention also includes a system for using ancillary processors and storage to speed time critical data captured.

Abstract: A method for using ancillary processors and memory to speed critical data capture, comprising: building a list of memory address ranges associated with a second partition, where the memory address ranges are located in central storage memory and contain the data to be captured; reading the data from the memory address ranges; and writing the data to a portion of memory reserved by a first partition as a capture pool, where the capture pool is also located in central storage memory and the capture pool is not accessible by said secondary partition. A system for implementing the method is also disclosed.

Abstract: In a computing system having swappable and non-swappable address spaces, wherein the computing system includes an operating system that includes a Real Storage Manager (RSM), a Systems Resource Manager (SRM) and a Region Control Task (RCT), a method for recovering swappable fixed non-preferred memory is provided which includes receiving a request from the operating system to configure an area of real memory to create an intercepted swappable address space, wherein the intercepted swappable address space includes a flagged fixed frame element identified for configuration, examining the intercepted swappable address space so as to determine if the intercepted swappable address space will remain swappable, requesting the SRM to coordinate the swapping process, quiescing the intercepted address space, generating a first return code responsive to the intercepted swappable address space remaining swappable, communicating the first return code to the RCT so as to cause the RCT to respond to the first return code, in

Abstract: Data is written to and read from a shared pipe by applications of multiple systems. At least one shared pipe is located within an external shared memory coupled to one or more central processing complexes. Each of the central processing complexes has one or more operating system images, which controls execution of one or more piping applications. At least one piping application corresponding to at least one operating system image writes data to a shared pipe located in the external shared memory and at least one other application corresponding to one or more other operating system images reads data from the same shared pipe, thereby providing cross-system data piping.

Abstract: Data is written to and read from a shared pipe by applications of multiple systems. At least one shared pipe is located within an external shared memory coupled to one or more central processing complexes. Each of the central processing complexes has one or more operating system images, which controls execution of one or more piping applications. At least one piping application corresponding to at least one operating system image writes data to a shared pipe located in the external shared memory and at least one other application corresponding to one or more other operating system images reads data from the same shared pipe, thereby providing cross-system data piping.

Abstract: Data is written to and read from a shared pipe by applications of multiple systems. At least one shared pipe is located within an external shared memory coupled to one or more central processing complexes. Each of the central processing complexes has one or more operating system images, which controls execution of one or more piping applications. At least one piping application corresponding to at least one operating system image writes data to a shared pipe located in the external shared memory and at least one other application corresponding to one or more other operating system images reads data from the same shared pipe, thereby providing cross-system data piping.