Patents by Inventor Roman Gouk
Roman Gouk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11927885Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.Type: GrantFiled: August 8, 2022Date of Patent: March 12, 2024Assignee: Applied Materials, Inc.Inventors: Roman Gouk, Jean Delmas, Steven Verhaverbeke, Chintan Buch
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Patent number: 11881447Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: GrantFiled: April 12, 2021Date of Patent: January 23, 2024Assignee: Applied Materials, Inc.Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park, Kyuil Cho, Kurtis Leschkies, Roman Gouk, Chintan Buch, Vincent Dicaprio, Bernhard Stonas, Jean Delmas
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Patent number: 11862546Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: GrantFiled: November 27, 2019Date of Patent: January 2, 2024Assignee: Applied Materials, Inc.Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park, Kyuil Cho, Kurtis Leschkies, Roman Gouk, Chintan Buch, Vincent Dicaprio
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Patent number: 11798903Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.Type: GrantFiled: April 20, 2022Date of Patent: October 24, 2023Assignee: Applied Materials, Inc.Inventors: Chintan Buch, Roman Gouk, Steven Verhaverbeke
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Patent number: 11705365Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.Type: GrantFiled: May 18, 2021Date of Patent: July 18, 2023Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Kurtis Leschkies, Roman Gouk, Giback Park, Kyuil Cho, Tapash Chakraborty, Han-Wen Chen, Steven Verhaverbeke
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Publication number: 20220375787Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Inventors: Wei-Sheng LEI, Kurtis LESCHKIES, Roman GOUK, Giback PARK, Kyuil CHO, Tapash CHAKRABORTY, Han-Wen CHEN, Steven VERHAVERBEKE
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Publication number: 20220373883Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.Type: ApplicationFiled: August 8, 2022Publication date: November 24, 2022Inventors: Roman GOUK, Jean DELMAS, Steven VERHAVERBEKE, Chintan BUCH
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Patent number: 11454884Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.Type: GrantFiled: April 15, 2020Date of Patent: September 27, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Roman Gouk, Jean Delmas, Steven Verhaverbeke, Chintan Buch
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Patent number: 11424137Abstract: Embodiments described herein generally relate to a processing chamber incorporating a small thermal mass which enable efficient temperature cycling for supercritical drying processes. The chamber generally includes a body, a liner, and an insulation element which enables the liner to exhibit a small thermal mass relative to the body. The chamber is also configured with suitable apparatus for generating and/or maintaining supercritical fluid within a processing volume of the chamber.Type: GrantFiled: May 20, 2019Date of Patent: August 23, 2022Assignee: Applied Materials, Inc.Inventors: Roman Gouk, Han-Wen Chen, Steven Verhaverbeke, Jean Delmas
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Publication number: 20220246558Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Applicant: Applied Materials, Inc.Inventors: Chintan Buch, Roman Gouk, Steven Verhaverbeke
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Publication number: 20220171281Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 ?m.Type: ApplicationFiled: February 17, 2022Publication date: June 2, 2022Inventors: Roman GOUK, Giback PARK, Kyuil CHO, Han-Wen CHEN, Chintan BUCH, Steven VERHAVERBEKE, Vincent DICAPRIO
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Patent number: 11315890Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.Type: GrantFiled: August 28, 2020Date of Patent: April 26, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Chintan Buch, Roman Gouk, Steven Verhaverbeke
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Patent number: 11281094Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 ?m.Type: GrantFiled: November 15, 2018Date of Patent: March 22, 2022Assignee: Applied Materials, Inc.Inventors: Roman Gouk, Giback Park, Kyuil Cho, Han-Wen Chen, Chintan Buch, Steven Verhaverbeke, Vincent Dicaprio
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Publication number: 20220051999Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.Type: ApplicationFiled: August 28, 2020Publication date: February 17, 2022Applicant: Applied Materials, Inc.Inventors: Chintan Buch, Roman Gouk, Steven Verhaverbeke
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Publication number: 20220044936Abstract: In an embodiment, a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer is provided. The method includes detecting the mask layer by a sensor, the mask layer providing a substrate surface; determining a property of the blind via, the property comprising one or more of a top diameter, a bottom diameter, a volume, or a taper angle; focusing a Gaussian laser beam, under laser process parameters, at the substrate surface to remove at least a portion of the mask layer; adjusting the laser process parameters based on the property; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. The mask layer can be pre-etched. Apparatus for forming a blind via in a substrate are also provided.Type: ApplicationFiled: October 22, 2021Publication date: February 10, 2022Inventors: Wei-Sheng LEI, Kurtis LESCHKIES, Roman GOUK, Steven VERHAVERBEKE, Visweswaren SIVARAMAKRISHNAN
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Patent number: 11232951Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.Type: GrantFiled: July 14, 2020Date of Patent: January 25, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Wei-Sheng Lei, Kurtis Leschkies, Roman Gouk, Steven Verhaverbeke, Visweswaren Sivaramakrishnan
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Publication number: 20220020590Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.Type: ApplicationFiled: July 14, 2020Publication date: January 20, 2022Inventors: Wei-Sheng LEI, Kurtis LESCHKIES, Roman GOUK, Steven VERHAVERBEKE, Visweswaren SIVARAMAKRISHNAN
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Publication number: 20210325776Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.Type: ApplicationFiled: April 15, 2020Publication date: October 21, 2021Inventors: Roman GOUK, Jean DELMAS, Steven VERHAVERBEKE, Chintan BUCH
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Patent number: 11133174Abstract: Embodiments described herein generally relate to a processing chamber having a reduced volume for performing supercritical drying processes or other phase transition processes. The chamber includes a substrate support moveably disposed on a first track and a door moveably disposed on a second track. The substrate support and door may be configured to move independently of one another and the chamber may be configured to minimize vertical movement of the substrate within the chamber.Type: GrantFiled: March 13, 2019Date of Patent: September 28, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Roman Gouk, Han-Wen Chen, Steven Verhaverbeke, Jean Delmas
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Publication number: 20210257289Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: ApplicationFiled: April 12, 2021Publication date: August 19, 2021Inventors: Han-Wen CHEN, Steven VERHAVERBEKE, Giback PARK, Kyuil CHO, Kurtis LESCHKIES, Roman GOUK, Chintan BUCH, Vincent DICAPRIO, Bernhard STONAS, Jean DELMAS