Patents by Inventor Romel Manatad
Romel Manatad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11735508Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: GrantFiled: November 4, 2021Date of Patent: August 22, 2023Assignee: SEMICONDUCTOR COMONENTS INDUTRIES, LLCInventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
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Publication number: 20220059443Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina ESTACIO
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Patent number: 11177203Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first conductive clip, where the first terminal of the inductor can be coupled with a contact pad of the first conductive clip. The second terminal of the inductor can be electrically coupled with the leadframe via a second conductive clip, where the second terminal of the inductor can be coupled with a contact pad of the second conductive clip. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: GrantFiled: February 19, 2019Date of Patent: November 16, 2021Assignee: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
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Publication number: 20190181083Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first conductive clip, where the first terminal of the inductor can be coupled with a contact pad of the first conductive clip. The second terminal of the inductor can be electrically coupled with the leadframe via a second conductive clip, where the second terminal of the inductor can be coupled with a contact pad of the second conductive clip. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: ApplicationFiled: February 19, 2019Publication date: June 13, 2019Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina ESTACIO
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Patent number: 10256178Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality of leads can be disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate. The assembly can being mounted on the leadframe. The apparatus can further include an inductor having a first terminal and a second terminal. The first terminal of the inductor can being coupled with the leadframe via a first contact pad, and the second terminal of the inductor can be coupled with the leadframe via a second contact pad. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: GrantFiled: August 31, 2017Date of Patent: April 9, 2019Assignee: Fairchild Semiconductor CorporationInventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
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Publication number: 20180068935Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality of leads can be disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate. The assembly can being mounted on the leadframe. The apparatus can further include an inductor having a first terminal and a second terminal. The first terminal of the inductor can being coupled with the leadframe via a first contact pad, and the second terminal of the inductor can be coupled with the leadframe via a second contact pad. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: ApplicationFiled: August 31, 2017Publication date: March 8, 2018Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina Estacio
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Patent number: 8624393Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.Type: GrantFiled: February 24, 2012Date of Patent: January 7, 2014Assignee: Fairchild Semiconductor CorporationInventors: Suku Kim, James Murphy, Matthew Reynolds, Romel Manatad, Jan Mancelita, Michael Gruenhagen
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Publication number: 20080036056Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.Type: ApplicationFiled: March 29, 2007Publication date: February 14, 2008Inventors: Rajeev Joshi, Consuelo Tangpuz, Romel Manatad
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Publication number: 20070241431Abstract: A semiconductor package is disclosed. The package includes a leadframe structure comprising a die attach region and plurality of leads. A molding material is molded around at least a portion of the leadframe structure, and comprises a window. A semiconductor die comprising an edge is mounted on the die attach region and is within the window. A gap is present between the edge of the semiconductor die and the molding material.Type: ApplicationFiled: March 22, 2007Publication date: October 18, 2007Inventor: Romel Manatad
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Patent number: 7256479Abstract: A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.Type: GrantFiled: January 13, 2005Date of Patent: August 14, 2007Assignee: Fairchild Semiconductor CorporationInventors: Jonathan A. Noquil, Connie Tangpuz, Romel Manatad, Stephen Martin, Rajeev Joshi, Venkat Iyer
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Publication number: 20070161151Abstract: The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.Type: ApplicationFiled: February 28, 2006Publication date: July 12, 2007Inventors: Ruben Madrid, Romel Manatad
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Publication number: 20060231933Abstract: A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.Type: ApplicationFiled: June 1, 2006Publication date: October 19, 2006Inventors: Elsie Cabahug, Marvin Gestole, Margie Tumulak-Rios, Lilith Montayre, Romel Manatad
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Publication number: 20060151861Abstract: A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.Type: ApplicationFiled: January 13, 2005Publication date: July 13, 2006Inventors: Jonathan Noquil, Connie Tangpuz, Romel Manatad, Stephen Martin, Rajeev Joshi, Venkat Iyer
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Publication number: 20050280126Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.Type: ApplicationFiled: August 25, 2005Publication date: December 22, 2005Inventors: Rajeev Joshi, Consuelo Tangpuz, Romel Manatad
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Publication number: 20050224940Abstract: A packaging assembly for semiconductor devices and a method for making such packaging is described. The invention provides a non-Pb bump design during a new flip-chip method of packaging. The design uses special conductive materials in a stud form, rather than a solder ball containing Pb. This configuration maintains a desirable solder thickness between the die and the leadframe and forms a high standoff by restricting solder wettabilty on the leadframe side. This configuration also absorbs any stress and protects the die from cracking. The invention also provides methods for making such semiconductor packages.Type: ApplicationFiled: June 3, 2005Publication date: October 13, 2005Inventors: Consuelo Tangpuz, Romel Manatad, Margie Rios, Erwin Cruz
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Publication number: 20050167848Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.Type: ApplicationFiled: November 5, 2003Publication date: August 4, 2005Applicant: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Consuelo Tangpuz, Romel Manatad