Patents by Inventor Ron Eliyahu
Ron Eliyahu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7518908Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.Type: GrantFiled: May 28, 2002Date of Patent: April 14, 2009Assignee: Saifun Semiconductors Ltd.Inventors: Eduardo Maayan, Ron Eliyahu, Boaz Eitan
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Patent number: 7512009Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.Type: GrantFiled: April 27, 2006Date of Patent: March 31, 2009Assignee: Saifun Semiconductors Ltd.Inventors: Eduardo Maayan, Ron Eliyahu, Ameet Lann, Boaz Eitan
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Publication number: 20080109594Abstract: A system and a method for operating a non-volatile memory (NVM) device including a micro-controller adapted to control peripheral circuitry associated with an NVM array. The method includes providing at least one operation command to the micro-controller of the NVM device and applying operating signals to peripheral circuitry of the NVM device to operate the NVM array based on at least one operation command. The system includes: (1) a NVM device with a NVM array adapted to store data and commands, peripheral circuitry adapted to operate the NVM array and a micro-controller adapted to control the peripheral circuitry; and (2) an external device to provide at least one command to the micro-controller of the NVM device.Type: ApplicationFiled: October 31, 2007Publication date: May 8, 2008Inventors: Meir Grossgold, Ron Eliyahu, Mori Edan, Yair Sofer
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Publication number: 20060268621Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.Type: ApplicationFiled: April 27, 2006Publication date: November 30, 2006Applicant: Saifun Semiconductors, Ltd.Inventors: Eduardo Maayan, Ron Eliyahu, Ameet Lann, Boaz Eitan
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Patent number: 7064983Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.Type: GrantFiled: June 5, 2003Date of Patent: June 20, 2006Assignee: Saifum Semiconductors Ltd.Inventors: Eduardo Maayan, Ron Eliyahu, Ameet Lann, Boaz Eitan
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Publication number: 20060036803Abstract: A system and a method for operating a non-volatile memory (NVM) device including a micro-controller adapted to control peripheral circuitry associated with an NVM array. The method includes providing at least one operation command to the micro-controller of the NVM device and applying operating signals to peripheral circuitry of the NVM device to operate the NVM array based on at least one operation command. The system includes: (1) a NVM device with a NVM array adapted to store data and commands, peripheral circuitry adapted to operate the NVM array and a micro-controller adapted to control the peripheral circuitry; and (2) an external device to provide at least one command to the micro-controller of the NVM device.Type: ApplicationFiled: August 16, 2004Publication date: February 16, 2006Inventors: Mori Edan, Meir Grossgold, Yair Sofer, Ron Eliyahu
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Publication number: 20040081010Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.Type: ApplicationFiled: June 5, 2003Publication date: April 29, 2004Inventors: Eduardo Maayan, Ron Eliyahu, Ameet Lann, Boaz Eitan
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Patent number: 6636440Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array, the method including refreshing a threshold voltage of a bit of a memory cell in an EEPROM array, the threshold voltage being different than a previous threshold voltage, by restoring the threshold voltage of the bit at least partially back to the previous threshold voltage.Type: GrantFiled: April 25, 2001Date of Patent: October 21, 2003Assignee: Saifun Semiconductors Ltd.Inventors: Eduardo Maayan, Ron Eliyahu, Shai Eisen, Boaz Eitan
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Patent number: 6614692Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of thief selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.Type: GrantFiled: January 18, 2001Date of Patent: September 2, 2003Assignee: Saifun Semiconductors Ltd.Inventors: Ron Eliyahu, Eduardo Maayan, Ilan Bloom, Boaz Eitan
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Patent number: 6584017Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is onboard the die containing the memory array, but not a cell within the memory array.Type: GrantFiled: April 5, 2001Date of Patent: June 24, 2003Assignee: Saifun Semiconductors Ltd.Inventors: Eduardo Maayan, Ron Eliyahu, Ameet Lann, Boaz Eitan
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Patent number: 6535434Abstract: An architecture and method for implementing a non-strobed operation on an array cell within a memory array in which a reference unit is provided for emulating the response of an array cell during a desired operation, for example, a read, program verify, erase verify or other types of read operations. The reference unit includes a reference cell which is driven by a non-strobed gate voltage. The architecture and method permit relatively noise-free array cell interrogations at close to ground voltage levels.Type: GrantFiled: April 5, 2001Date of Patent: March 18, 2003Assignee: Saifun Semiconductors Ltd.Inventors: Eduardo Maayan, Yair Sofer, Ron Eliyahu, Boaz Eitan
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Publication number: 20030039153Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.Type: ApplicationFiled: May 28, 2002Publication date: February 27, 2003Inventors: Eduardo Maayan, Ron Eliyahu, Boaz Eitan
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Publication number: 20020191465Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array, the method including refreshing a threshold voltage of a bit of a memory cell in an EEPROM array, the threshold voltage being different than a previous threshold voltage, by restoring the threshold voltage of the bit at least partially back to the previous threshold voltage.Type: ApplicationFiled: April 25, 2001Publication date: December 19, 2002Inventors: Eduardo Maayan, Ron Eliyahu, Shai Eisen, Boaz Eitan
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Publication number: 20020145911Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is onboard the die containing the memory array, but not a cell within the memory array.Type: ApplicationFiled: April 5, 2001Publication date: October 10, 2002Inventors: Eduardo Maayan, Ron Eliyahu, Ameet Lann, Boaz Eitan
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Publication number: 20020145918Abstract: An architecture and method for implementing a non-strobed operation on an array cell within a memory array in which a reference unit is provided for emulating the response of an array cell during a desired operation, for example, a read, program verify, erase verify or other types of read operations. The reference unit includes a reference cell which is driven by a non-strobed gate voltage. The architecture and method permit relatively noise-free array cell interrogations at close to ground voltage levels.Type: ApplicationFiled: April 5, 2001Publication date: October 10, 2002Applicant: SAIFUN SEMICONDUCTORS LTD.Inventors: Eduardo Maayan, Yair Sofer, Ron Eliyahu, Boaz Eitan
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Publication number: 20020132436Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.Type: ApplicationFiled: January 18, 2001Publication date: September 19, 2002Inventors: Ron Eliyahu, Eduardo Maayan, Ilan Bloom, Boaz Eitan
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Patent number: 6014761Abstract: In an (de)-interleaver (201) for J long subsequences (640-646) of data units (612), FIFOs are mapped into a memory (245) in such a way that locations (240) needed for one FIFO are moving through the memory (245). A generator (208) modulo increments only a single pointer (p, 230) which activates memory locations (240-p). Thereby, increments .DELTA.j correspond to FIFO sizes. For some p, (de)-interleaver (201) reads (25) a data unit (612) from a location (240) and than writes a new data unit (612) into that location (240), thus saving set-up times to establish a pointer. Also, the (de)-interleaver (201) needs only a number of memory locations K=(D-1 ) corresponding to a (D-1) interleaving depth. The (de)-interleaver (201) as part of a system (200) is fully programmable and can transfer data in two directions. Also, (de-) interleaving parameters (D-1) and J can be reconfigured during data transmission.Type: GrantFiled: October 6, 1997Date of Patent: January 11, 2000Assignee: Motorola, Inc.Inventors: Oded Lachish, Ron Eliyahu, Marc Neustadter
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Patent number: 5923658Abstract: An ATM line card is provided wherein a microprocessor bus is selectively coupled to a memory bus during maintenance time intervals. This allows direct transfer of connection memory data to the microprocessor system of the line card and thus to the RAM of the system. After the transfer is accomplished the busses are decoupled again so that further maintenance work of the connection memory and the transferred data can be done independently. If the access to the connection memory is due to a destructive read operation the corresponding memory locations in the connection memory are reset simultaneous to the transfer of the data which are read out from the DMA of the microprocessor system to the RAM. This results in a dramatic reduction of the time required for maintenance of the ATM system.Type: GrantFiled: May 15, 1997Date of Patent: July 13, 1999Assignee: Motorola Inc.Inventors: Ronen Shtayer, Ron Eliyahu