Abstract: A method for measuring the width and profile of structures in a semiconductor wafer comprises the step of constructing test structures on the wafer shaped to function as moats for confining electrically conductive liquid. The moats have an elongated shape. By measuring the electrical resistance exhibited by the liquid within the moat, the dimensions of the moat and, thus, the other structures on the wafer can be measured. In an alternative embodiment, the conductive liquid is used to facilitate electrical contact to the various structures formed in the wafer.

Abstract: A method for measuring the width of structures in a semiconductor wafer comprises the step of constructing test structures on the wafer shaped to function as moats for confining electrically conductive liquid. The moats have an elongated shape. By measuring the electrical resistance exhibited by the liquid within the moat, the dimensions of the moat and, thus, the other structures on the wafer can be measured.

Abstract: Circuitry, including a non-volatile dynamic random access memory cell, a sense amplifier and a data latch affords non-destructive accessing and comparison of the data stored within the volatile and non-volatile portion of the memory cell. In certain applications, it is desirable to restore the volatile data to the volatile portion of the memory cell, and the circuitry also provides a path for such restoration.

Abstract: A memory cell providing separate storage of volatile and non-volatile data. The volatile and non-volatile data elements, which are not necessarily duplicative, can be non-destructively accessed within a single memory clock cycle via separate volatile and non-volatile bit lines. The cell stores volatile data by the storage of charge on a dynamic storage capacitor formed of a semiconductor device and stores non-volatile data by the storage of charge in the floating gate of a transistor. An array of the memory cells illustrates comparison of the volatile and non-volatile data elements within a single memory cycle particularly suited for pattern recognition.

Abstract: A non-volatile dynamic RAM circuit where each memory cell includes an access transistor, a floating gate structure, and a recall transistor connected in series between an I/O bit line and a common line. A conducting plate and storage node of the floating gate structure functions as the volatile storage element of the cell and the floating gate functions as the non-volatile storage element.

Abstract: Resistive elements of semiconductor devices and integrated circuits are reduced in size thereby allowing larger scale integration. Deep level dopants including impurities or crystalline lattice defects, or both, are formed in a low resistance doped region thereby increasing the resistance of a portion of the doped region. Resistive contacts and interconnects require less semiconductor surface area.