Patents by Inventor Ron Sartschev

Ron Sartschev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9503065
    Abstract: Example circuitry includes: a first sampling circuit configured to operate based on a first clock signal, to receive data, and to sample the data, where the first clock signal is calibrated to compensate for a first timing error in a rising edge of the data; a second sampling circuit configured to operate based on a second clock signal, to receive the data, and to sample the data, where the second first clock signal is calibrated to compensate for a second timing error in a falling edge of the data; and a third sampling circuit to receive the data and a third clock signal, to sample the data based on the third clock signal to produce sampled data, and to control an output of the circuitry based on the sampled data to be either an output of the first sampling circuit or an output of the second sampling circuit.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 22, 2016
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Antonie van der Wagt, Ron Sartschev, Bradley A Phillips
  • Patent number: 7403030
    Abstract: An apparatus for providing current to a device under test includes a first parametric measurement unit configured to provide current to the device, and a second parametric measurement unit configured to provide current to the device. The current from the second parametric measurement unit augments the current from the first parametric measurement unit at the device.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: July 22, 2008
    Assignee: Teradyne, Inc.
    Inventors: Ernest Walker, Ron Sartschev
  • Patent number: 7271610
    Abstract: Circuitry for use in testing a device includes a first measurement unit to apply a forced voltage to the device, and a second measurement unit having functionality that is disabled. The second measurement unit includes a sense path to receive a sensed voltage from the device, where the sense path connects to the first measurement unit through the second measurement unit. The first measurement unit adjusts the forced voltage based on the sensed voltage.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: September 18, 2007
    Assignee: Teradyne, Inc.
    Inventors: Ernest Walker, Ron Sartschev
  • Publication number: 20060132166
    Abstract: A method of and system for producing signals to test semiconductor devices includes a pin electronic (PE) stage for providing a parametric measurement unit (PMU) current test signal to a semiconductor device under test. The PE stage also senses a response from the semiconductor device under test.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 22, 2006
    Inventors: Ernest Walker, Ron Sartschev
  • Publication number: 20060132164
    Abstract: Circuitry for use in testing a device includes a first measurement unit to apply a forced voltage to the device, and a second measurement unit having functionality that is disabled. The second measurement unit includes a sense path to receive a sensed voltage from the device, where the sense path connects to the first measurement unit through the second measurement unit. The first measurement unit adjusts the forced voltage based on the sensed voltage.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Inventors: Ernest Walker, Ron Sartschev
  • Publication number: 20060132163
    Abstract: An apparatus for providing current to a device under test includes a first parametric measurement unit configured to provide current to the device, and a second parametric measurement unit configured to provide current to the device.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Inventors: Ernest Walker, Ron Sartschev