Abstract: The instant disclosure relates to contact grids for use in photovoltaic cells, wherein a cross-section of the contact grid fingers is shaped as a trapezoid, as well as a method of making photovoltaic cells comprising these contact grids. The contact grids of the instant disclosure are cost effective and, due to their thick metal grids, exhibit minimum resistance. Despite having thick metal grids, the unique shape of the contact grid fingers of the instant disclosure allow the photovoltaic cells in which they are employed to retain more solar energy than traditional solar cells by reflecting incoming solar energy back onto the surface of the solar cell instead of reflecting this energy away from the cell.

Abstract: The instant disclosure relates to contact grids for use in photovoltaic cells, wherein a cross-section of the contact grid fingers is shaped as a trapezoid, as well as a method of making photovoltaic cells comprising these contact grids. The contact grids of the instant disclosure are cost effective and, due to their thick metal grids, exhibit minimum resistance. Despite having thick metal grids, the unique shape of the contact grid fingers of the instant disclosure allow the photovoltaic cells in which they are employed to retain more solar energy than traditional solar cells by reflecting incoming solar energy back onto the surface of the solar cell instead of reflecting this energy away from the cell.

Abstract: A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting the bond pads to the Ni/Au pad metallization.

Abstract: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.

Abstract: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract: An electroless touch-up process for repairing copper metallization deposited in dual damascene structures with high aspect ratios. An initial copper strike layer is produced by directional deposition techniques such that discontinuous sidewall coverage occurs. An evolutionary electroless touch-up process then proceeds to conformally grow the copper layer on all surfaces. The result of the evolutionary process is to produce a continuous copper strike layer that can be used with conventional electroplating techniques.

Abstract: A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

Abstract: Method for treating surface of dielectric polymer with water vapor plasma to form reactive sites and grafting a reactive polymer thereto to tailor the properties of the dielectric polymer surface.

Abstract: A process is disclosed for producing a metal-organic polymer combination by contacting the polymer with a plasma followed by an aqueous solution of a metal salt. In one embodiment a water or nitrous oxide plasma is used to treat a polyimide or a fluorinated polymer. The polymer is combined with a metal cation, the metal being a catalyst for a conventional electroless coating after which it is contacted with an electroless metal plating bath for the formation of electrical circuits and especially for plating high aspect ratio vias in microcircuits. Unlike the conventional electroless process, the cationic catalytic metal is not reduced to a zero valent metal catalyst prior to the application of the electroless metal coating solution.The process also improves the wettability of the polymer, especially the fluorinated polymer and is especially useful in improving the wettability of high aspect ratio vias.

Abstract: Method for pressing a material into a through-hole or blind-hole in a substrate. The material is disposed on the surface of the substrate. An environment is provided permitting the material to flow for example by heating the material to the glass transition temperature or above. Thereafter pressure is applied causing the material to flow, first coating the sidewall of the hole and on the continued application of pressure the material flows to completely fill the hole. The resulting substrate can have a substantially planar surface having holes with the periphery coated with or completely filled with the material. The material is preferably a thermoplastic polymeric material such as a polyimide and a perfluorinated polymer.

Abstract: A method for seeding the surface of a polyimide film which has been generated from a precursor polyamic acid film comprising the steps of: generating a film of polyamic acid on a substance (which may be done by conventional spin coating or by other solution coating techniques well known in the art); then either exposing the polyamic acid film to a solution containing palladium cations; heat-treating the palladium-treated film in a time/temperature schedule that causes imidization of the polymer to occur; exposing the seeded film to an electroless plating bath which causes the deposition of blanket metal film on the surface of the polymer film; or curing the film to the polyimide form; mechanically abrading the film surface, exposing the film to a solution containing palladium cations; exposing the seeded film to an electroless plating bath which causes the deposition of blanket metal film on the surface of the polymer film.

Abstract: Method for water vapor plasma treating the surface of a polymer body to enhance the adhesion of a first and second polymer surface. The method is particularly useful for polyimide surfaces.