Abstract: A single chip audio system 100 includes a bus interface 101, digital to analog converters 110, an analog mixer 115, and analog spatial enhancement circuitry 7500. Digital to analog converters 110 convert digital audio data received through bus interface 101 into analog signals. Analog mixer 115 mixes signals received from digital to analog converters 110 with an analog signal received from an external source. Analog spatial enhancement circuitry 7500 enhances first and second mixed analog signals output from analog mixer 115.

Abstract: Amplitude control circuitry 5000 includes a first register 5001 for storing received amplitude control data and a second register 5002 for storing amplitude control data transfered from first register 5001. Output circuitry 5005, 5006, 5007 controls the amplitude of a received signal in response to amplitude data transferred from second register. A sensor 5003 determines when data stored in first register 5001 and second register 5002 does not match and enables a comparator 5004 when data in first register 5001 and, second register 5002 does not match. Comparator 5004 compares a signal output from output circuitry 5005, 5006, 5007 with a reference signal and generates a signal for enabling the transfer of data from first register 5001 to second register 5002 when the signal output from output circuitry 5005, 5006, 5007 falls within a window defined by the reference voltage.

Abstract: A single chip audio system 100 includes a bus interface 101, digital to analog converters 110, an analog mixer 115, and analog spatial enhancement circuitry 7500. Digital to analog converters 110 convert digital audio data received through bus interface 101 into analog signals. Analog mixer 115 mixes signals received from digital to analog converters 110 with an analog signal received from an external source. Analog spatial enhancement circuitry 7500 enhances first and second mixed analog signals output from analog mixer 115.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: An audio system 100 disposed on a single chip includes an output mixer 115 having inputs for receiving first digital audio data of a first bit width from a first digital-to-analog converter 110, digital audio data of a second bit width from a second digital-to-analog converter 6601, and analog data from an external port. An output port drives an analog signal output from the output mixer. An input mixer 114 has inputs for receiving analog data from a plurality of sources and analog-to-digital converters 111 to convert an analog output from the input mixer into digital data. An input path transmits the digital data output from the analog to digital convertors 111 to an external digital bus.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A color synchronizer and windowing system for use in a video or video/graphics system which uses digital television technology integrated circuits to digitize the video information. The digitized video information is stored in a frame buffer as luminance and chrominance data samples. The frame buffer also stores a chrominance reference synchronization signal which is synchronized to the digitized chrominance data samples so as to properly identify the boundary for each chrominance data sample; wherein each such chrominance data sample is associated with a plurality of luminance data samples. This encoded data insures that the luminance and chrominance data samples are properly decoded on chrominance data sample boundaries even though the synchronization signal normally associated with the digital television technology integrated circuits is not available due to the storage of the luminance and chrominance data samples within the frame buffer.

Abstract: Data to be stored in a frame buffer (12) that stores data representing an image are drawn from a look-up table (34). The look-up table (34) contains conversion data and is addressed by the output of a multiplexer circuit (24). The multiplexer circuit (24) receives its inputs from the data output port of the frame buffer (12), from a register (42), and from an analog-to-digital converter (22) that converts the output of a video camera (20) to digital signals. In response to different values on selection-signal lines (36), the multiplexer circuit (24) assembles the address that it applies to the look-up table (34) from different combinations of the outputs of the frame buffer (12), the register (42), and the analog-to-digital-converter (22).