Abstract: A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Abstract: A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options.Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented.

Abstract: A method and apparatus for characterizing the quality of an electrically thin semiconductor film and its interfaces with adjacent materials by employing a capacitor and a topside electrical contact on the same side of the electrically thin semiconductor film to thereby permit the taking of capacitance-voltage (C-V) measurements. A computer controlled C-V measuring system is operatively coupled to the contact and capacitor to modulate the potential on the capacitor. Variation of the voltage applied to the capacitor enables modulation of the potential applied to the film to thereby vary the conductivity of the film between the capacitor gate node and the topside contact.

Abstract: A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

Abstract: A dual-polarity nonvolatile MOS analog memory cell is disclosed that comprises two pairs of complementary metal oxide field effect transistors. Each pair includes a p-channel and an n-channel transistor. The gates of each transistor are all operably coupled in common to form a common floating gate. The sources of the transistors of the first transistor pair are operably coupled to a common ground. The sources of the second pair of transistors are operably coupled together to form an output junction. Positive voltage applied to the drain of the n-channel transistor of the first transistor pair causes a positive analog value to be stored in memory when there previously was no value stored in memory, or increases a value previously stored in memory. Negative voltage applied to the drain of the p-channel transistor of the first transistor pair causes a negative analog value to be stored in memory when there previously was no value stored in memory, or decreases a value previously stored in memory.

Abstract: An integrated injection logic device formed on an insulating substrate. A lateral, load transistor and an adjacent, vertical switching transistor are formed in the semiconductor layer such that the collector region of the lateral transistor coincides with the base region of the switching transistor. The emitter of the switching transistor is located at the surface of the semiconductor injecting carriers downward into the collector. Isolated multiple collector contacts required for wired-AND logic are obtained by using separate Schottky-barrier contacts for each collector output.

Abstract: An apparatus and method for improving VLSI and VHSIC system data transmission relies on a plurality of optoelectronic switches actuated by pulses from at least one light source, a laser. Differing lengths of optical fibers couple the pulsed light from the laser at different times to create a sequence of actuation light pulses for the plurality of optoelectronic switches each time the light source is pulsed. Thus the information appearing at a plurality of parallel data nodes is converted to serial form at an output bonding pad on the chip. Optionally, a similar pulsing of electrooptic switches coupled to an input bonding pad converts serial data to parallel form. Faster input and output switching times are provided, reliability and complexity are reduced, particularly as compared to off-chip coupling arrangements, and power consumption and dissipation are reduced.

Abstract: An optical wavelength demultiplexer is fabricated as an integral part of an integrated circuit chip. A waveguide in a common substrate having a chirped diffraction grating receives a number of wavelengths of optically modulated data from a single mode fiber. The wavelengths are diffracted from the plane of the lines of the grating into discrete beams angles through the substrate and impinge on appropriately located photodetectors. Signals provided by the detectors are fed to and processed by other integrated circuitry also contained on the chip. The common transparent substrate such as fused silica, glass, sapphire, lithium niobate or lithium tantalate mount semiconductor films of Si, Ge, GaAs or quanternary alloys that have the detectors and other integrated circuitry that are created by conventional CVD techniques.

Abstract: This invention relates to a process of manufacturing an integrated structure in which optical signals can be processed in an electrooptic material such as lithium tantalate and electrical signals can be processed in a semiconductor material such as silicon. Microelectronic semiconductors are fabricated in the semiconductor material and electrooptic devices are fabricated in the electrooptic material. Devices made by the process of the present invention are also disclosed.