Abstract: A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.

Abstract: A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.

Abstract: A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.

Abstract: A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.

Abstract: A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.

Abstract: An industrial automation controller module includes a main module and an energy storage module (ESM) releasably connected to the main module. The ESM includes a back-up electrical power source such as a battery or a capacitor that is electrically connected to processor circuitry of the main module when the ESM is physically connected to the main module. In case of interruption of operating power to the processor circuitry of the main module, the back-up power source of the ESM supplies back-up power to the main module to allow for completion of an emergency save operation to save data to non-volatile memory in the main module. If the ESM includes a capacitor back-up power source, it is charged by the main module and the capacitor charge is dissipated if the ESM is separated from the main module.

Abstract: The present invention provides a hardware implemented connection monitoring system. A timer array establishes an input timer and an output timer for each connection between the processor and each I/O connection. A state machine periodically steps through the timer array to update the accumulated values of the timers and to monitor if any of the timers has reached a preset, timer done value. If a timer reaches the timer done value, the state machine loads the timer status into an event buffer and generates an interrupt for the processor. The processor reads the event buffer, identifies whether the expired timer was an input timer or an output timer, and takes action accordingly.

Abstract: A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.

Abstract: A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.

Abstract: A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.

Abstract: An industrial automation controller module includes a main module and an energy storage module (ESM) releasably connected to the main module. The ESM includes a back-up electrical power source such as a battery or a capacitor that is electrically connected to processor circuitry of the main module when the ESM is physically connected to the main module. In case of interruption of operating power to the processor circuitry of the main module, the back-up power source of the ESM supplies back-up power to the main module to allow for completion of an emergency save operation to save data to non-volatile memory in the main module. If the ESM includes a capacitor back-up power source, it is charged by the main module and the capacitor charge is dissipated if the ESM is separated from the main module.

Abstract: An electronic module and chassis/module installation and cooling method are disclosed. The installation comprises a chassis including a metallic heat input region. An electronic module including an electronic component is adapted to be connected to the chassis. An uninterrupted thermal pathway thermally connects the electronic component of the module to the heat input region of the chassis. The thermal pathway comprises a chimney, a heat channel thermally connected to the chimney, and a heat output block thermally connected to the heat channel. A first electrically insulative non-metallic layer thermally couples the chimney to the electronic component. A second electrically insulative non-metallic layer thermally couples the heat output block to the chassis heat input region.

Abstract: The present invention relates to a system and methodology to mitigate memory current requirements in an industrial controller and to facilitate efficient on-line editing, storage and retrieval of user programs and data. A segmented memory architecture is provided, wherein a first memory segment is loaded with programmed instructions and other data that is relatively static in nature. A second memory segment is provided for storage of dynamic information such as controller data table variables that change frequently and/or rapidly during program execution of the controller. An execution memory is concurrently loaded with the user program to facilitate high performance program execution and to enable on-line edits of the user program during operation of the controller.

Abstract: An electronic module and chassis/module installation and cooling method are disclosed. The installation comprises a chassis including a metallic heat input region. An electronic module including an electronic component is adapted to be connected to the chassis. An uninterrupted thermal pathway thermally connects the electronic component of the module to the heat input region of the chassis. The thermal pathway comprises a chimney, a heat channel thermally connected to the chimney, and a heat output block thermally connected to the heat channel. A first electrically insulative non-metallic layer thermally couples the chimney to the electronic component. A second electrically insulative non-metallic layer thermally couples the heat output block to the chassis heat input region.

Abstract: An electronic module and chassis/module installation are disclosed. The installation comprises a chassis including a metallic heat input region. An electronic module including an electronic component is adapted to be connected to the chassis. An uninterrupted thermal pathway thermally connects the electronic component of the module to the heat input region of the chassis. The thermal pathway comprises a chimney, a heat channel thermally connected to the chimney, and a heat output block thermally connected to the heat channel. A first electrically insulative non-metallic layer thermally couples the chimney to the electronic component. A second electrically insulative non-metallic layer thermally couples the heat output block to the chassis heat input region.

Abstract: An electronic module and chassis/module installation are disclosed. The installation comprises a chassis including a metallic heat input region. An electronic module including an electronic component is adapted to be comnected to the chassis. An uninterrupted thermal pathway thermally connects the electronic component of the module to the heat input region of the chassis. The thermal pathway comprises a chimney, a heat channel thermally connected to the chimney, and a heat output block thermally connected to the heat channel A first electrically insulative non-metallic layer thermally couples the chimney to the electronic component. A second electrically insulative non-metallic layer thermally couples the heat output block to the chassis heat input region.

Abstract: A method for identifying memory modifications includes designating a first portion of a first memory as read-only. An abort condition is identified responsive to receiving a write instruction having a target address within the first portion. In response to the abort condition, a second portion of the first memory including at least the target address is flagged as being modified. The write instruction is executed.

Abstract: A system and method for industrial control I/O forcing is provided. The invention includes a processor, shared memory and an I/O processor with cache memory. The invention provides for the cache memory to be loaded with I/O force data from the shared memory. The I/O processor performs I/O forcing utilizing the I/O force data stored in the cache memory. The invention further provides for the processor to notify the I/O processor in the event that I/O force data is altered during control program execution. The invention further provides for the I/O processor to refresh the cache memory (e.g., via a blocked write) after receipt of alteration of the I/O force data from the processor.

Abstract: A system and method for industrial control I/O forcing is provided. The invention includes a processor, shared memory and an I/O processor with cache memory. The invention provides for the cache memory to be loaded with I/O force data from the shared memory. The I/O processor performs I/O forcing utilizing the I/O force data stored in the cache memory. The invention further provides for the processor to notify the I/O processor in the event that I/O force data is altered during control program execution. The invention further provides for the I/O processor to refresh the cache memory (e.g., via a blocked write) after receipt of alteration of the I/O force data from the processor.

Abstract: An integrated RISC and relay ladder logic processor uses shared registers, program counter, bus lines, and processing circuitry to eliminate delays associated with transfer of control in co-processor type architecture. The RISC instructions do not significantly interfere with the specialized hardware needed for rapid relay logic execution, the latter which may be further improved through the use of a pipeline well suited for relay ladder logic which creates few pipeline hazards. Two levels of condition codes are used for the arithmetic and logic instructions to permit nested arithmetic operations without interference with those instructions visible to the user. Hybrid instructions are provided to synchronize the relay ladder instructions with the arithmetic instructions, thus truly integrating the two instruction sets.