Abstract: An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter (HCA). The apparatus, system and method ensures that each operating system is unaware that the HCA hardware resources are being shared with other operating systems and further guarantees that the individual operating systems are prevented from accessing HCA hardware resources which are associated with other operating systems.

Abstract: A method, apparatus and computer program product are provided for implementing dynamic Virtual Lane buffer reconfiguration in a channel adapter. A first register is provided for communicating an adapter buffer size and allocation capability for the channel adapter. At least one second register is provided for communicating a current port buffer size and one second register is associated with each physical port of the channel adapter. A plurality of third registers is provided for communicating a current VL buffer size, and one third register is associated with each VL of each physical port of the channel adapter. The second register is used for receiving change requests for adjusting the current port buffer size for an associated physical port. The third register is used for receiving change requests for adjusting the current VL buffer size for an associated VL.

Abstract: An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With the present invention, a first level of access is provided through virtual address translation and a mechanism for determining if the requestor of access may access a system memory address space page associated with a real address to which the virtual address maps. A second level of access is provided through the allocation of usage classes and determining a required usage class for accessing an HCA facility.

Abstract: A method and apparatus for accessing a memory. Access rights for a memory operation are verified using a first data structure in response to receiving a request to perform the operation, wherein the request includes a virtual address for the operation. Responsive to access rights being verified for the memory operation, the virtual address translated into a real address using a second data structure.

Abstract: Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.

Abstract: An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter (HCA). The apparatus, system and method ensures that each operating system is unaware that the HCA hardware resources are being shared with other operating systems and further guarantees that the individual operating systems are prevented from accessing HCA hardware resources which are associated with other operating systems.

Abstract: An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With the present invention, a first level of access is provided through virtual address translation and a mechanism for determining if the requestor of access may access a system memory address space page associated with a real address to which the virtual address maps. A second level of access is provided through the allocation of usage classes and determining a required usage class for accessing an HCA facility.

Abstract: A processor system includes an I/O bus to host bridge in which I/O address translation elements are shared across multiple I/O bus bridges. A TCE manager is provided for retaining in cache a TCE entry associated with a discarded channel for association with a new channel responsive to a subsequent read request for a memory page referenced by the TCE entry.

Abstract: A method, system and program for controlling access to memory areas within a computer are provided. The invention comprises placing a first Bind Work Queue Element (WQE) at the head of a work queue, wherein the first Bind WQE defines parameters associated with a first Memory Window. A set of Work Requests is then placed on the work queue, behind the first Bind WQE wherein the work requests invoke operations that access the first Memory Window. A second Bind WQE is then placed on the work queue, behind the first set of Work Requests. This second Bind WQE defines parameters associated with a second Memory Window. A second set of Work Requests is placed on the work queue behind the second Bind WQE and invoke operations that access the second memory window. The Memory Windows can be associated with a common Memory Region and have different addresses and lengths or different access rights. In another embodiment, the first and second Memory Windows can be associated with different Memory Regions.

Abstract: A method, system and program for controlling access to computer memory are provided. The present invention comprises receiving a work request from a user, wherein the work request comprises an index portion and a protection portion. The index portion of the work request is used to locate an element in an address translation and protection table. The protection portion of the work request is then compared with a protection key in the table element, and access to memory is granted only if the protection portion and protection key match.

Abstract: An ordering mechanism, ordering method and computer program product are provided for implementing PCI local bus (PCI) peer to peer functions. When a read command is received, checking for available resource is performed. Responsive to not identifying available resource, a retry read command is sent. Responsive to sending the read command; checking for the retry read received command is provided. Responsive to identifying the retry read received command, the read command is resent.

Abstract: A method, system and program for controlling access to computer memory are provided. The present invention comprises receiving a work request from a user, wherein the work request comprises an index portion and a protection portion. The index portion of the work request is used to locate an element in an address translation and protection table. The protection portion of the work request is then compared with a protection key in the table element, and access to memory is granted only if the protection portion and protection key match.

Abstract: A method, system and program for controlling access to memory areas within a computer are provided. The invention comprises placing a first Bind Work Queue Element (WQE) at the head of a work queue, wherein the first Bind WQE defines parameters associated with a first Memory Window. A set of Work Requests is then placed on the work queue, behind the first Bind WQE wherein the work requests invoke operations that access the first Memory Window. A second Bind WQE is then placed on the work queue, behind the first set of Work Requests. This second Bind WQE defines parameters associated with a second Memory Window. A second set of Work Requests is placed on the work queue behind the second Bind WQE and invoke operations that access the second memory window. The Memory Windows can be associated with a common Memory Region and have different addresses and lengths or different access rights. In another embodiment, the first and second Memory Windows can be associated with different Memory Regions.

Abstract: A method and apparatus for accessing a memory. Access rights for a memory operation are verified using a first data structure in response to receiving a request to perform the operation, wherein the request includes a virtual address for the operation. Responsive to access rights being verified for the memory operation, the virtual address translated into a real address using a second data structure.

Abstract: A method, system, and apparatus for processing foreign protocol requests, such as PCI transactions, across a system area network (SAN) utilizing a data packet protocol is provided while maintaining the other SAN traffic. In one embodiment, a HCA receives a request for a load or store operation from a processor to an I/O adapter using a protocol which is foreign to the system area network, such as a PCI bus protocol. The HCA encapsulates the request into a data packet and places appropriate headers and trailers in the data packet to ensure that the data packet is delivered across the SAN fabric to an appropriate TCA to which the requested I/O adapter is connected. The TCA receives the data packet, determines that it contains a foreign protocol request, and decodes the data packet to obtain the foreign protocol request. The foreign protocol request is then transmitted to the appropriate I/O adapter.

Abstract: A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.

Abstract: A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize a data buffer with a priority-based data storage capability to handle incoming data from a plurality of available data sources. With such a capability, different relative priority levels are assigned to data associated with different data sources. Such priority levels are then used by control logic coupled to the buffer to control whether or not incoming data is stored (or optionally discarded) in the buffer. In particular, the relative priority of incoming data is compared with that associated with data currently stored in the buffer, with the incoming data being stored in the buffer only when its relative priority exceeds that of the currently-stored data.

Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency.