Patents by Inventor Ronald G. Walther

Ronald G. Walther has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7882454
    Abstract: A method for implementing improved observability of random resistant logic included in an integrated circuit (IC) design includes configuring a multiplexer device to pass, to a preexisting storage latch within the design, one of: a signal from one or more observation points within the random resistant logic and an output of first preexisting combinational logic; and selecting a preexisting net within the IC design to generate a randomized logic signal that, in a test mode, is passed to the multiplexer device to serve as a control signal thereto; wherein, in the test mode, the existing storage latch captures data randomly selected from either the existing combinational logic and the one or more observation points and in a normal mode, the existing storage latch captures data from only the existing combinational logic, facilitating random testing of the random resistant logic in a manner that avoids adding latches to the design.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mary P Kusko, Haoxing Ren, Ronald G Walther, Rona Yaari
  • Publication number: 20090271671
    Abstract: A method for implementing improved observability of random resistant logic included in an integrated circuit (IC) design includes configuring a multiplexer device to pass, to a preexisting storage latch within the design, one of: a signal from one or more observation points within the random resistant logic and an output of first preexisting combinational logic; and selecting a preexisting net within the IC design to generate a randomized logic signal that, in a test mode, is passed to the multiplexer device to serve as a control signal thereto; wherein, in the test mode, the existing storage latch captures data randomly selected from either the existing combinational logic and the one or more observation points and in a normal mode, the existing storage latch captures data from only the existing combinational logic, facilitating random testing of the random resistant logic in a manner that avoids adding latches to the design.
    Type: Application
    Filed: April 28, 2008
    Publication date: October 29, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Haoxing Ren, Ronald G. Walther, Rona Yaari
  • Patent number: 4992732
    Abstract: Method and apparatus for inspecting weld seams by means of particles of magnetizable material which align themselves in a magnetic field in a manner characteristic of faults the particles are suspended at the start of a test in a first liquid Fl.sub.1, the particles being freely mobile in the suspension and no viscosity change of the suspension taking place. Thereafter a substance is added to the suspension which effects a change of state, the particles aligned in the magnetic field thereby being fixed in their position.
    Type: Grant
    Filed: May 1, 1989
    Date of Patent: February 12, 1991
    Assignee: Magfoil & It GmbH
    Inventors: Karl G. Walther, Ronald G. Walther
  • Patent number: 4888745
    Abstract: For marking and finding weld seams to be investigated under water ultrasonic transmitters 54 are provided which have luminous or light-reflecting characters 58. The diver brings an ultrasonic receiver 60 up to the ultrasonic transmitter 54. For more exact location determination along the weld seam 52 a tape is provided which is disposed along the weld seam 52 and has elements arranged in coded manner.
    Type: Grant
    Filed: September 20, 1988
    Date of Patent: December 19, 1989
    Assignee: Magfoil & Inspektionstechniken GmbH
    Inventors: Karl G. Walther, Ronald G. Walther
  • Patent number: 4277699
    Abstract: A shift register latch circuit (FIG. 1) comprised of a polarity hold latch 1 connected to a set/reset latch 2. The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input S to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a `D` type edge trigger by connecting the clock input +B of the set/reset latch 2 to the clock -C supplied to the polarity hold latch 1. By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.
    Type: Grant
    Filed: July 26, 1979
    Date of Patent: July 7, 1981
    Assignee: International Business Machines Corporation
    Inventors: David J. Brown, Ronald G. Walther, Thomas W. Williams, Michael D. Wrigglesworth