Abstract: Provided are embodiments that include a system configured to generate executable code with protection barrier instructions. The system includes a storage medium, the storage medium being coupled to a processor. The processor is configured to analyze code, mark one or more potentially unsafe instructions in the code, and identify one or more unsafe instructions from the marked one or more potentially unsafe instructions in the code. The processor is also configured to insert a protection barrier instruction into the code based at least in part on identifying the one or more unsafe instructions, and translate the code, responsive to inserting the protection barrier instruction. Also provided are embodiments for a computer-implemented method and a computer program product for generating executable code with protection barrier instructions.

Abstract: Provided are embodiments that include a system configured to generate executable code with protection barrier instructions. The system includes a storage medium, the storage medium being coupled to a processor. The processor is configured to analyze code, mark one or more potentially unsafe instructions in the code, and identify one or more unsafe instructions from the marked one or more potentially unsafe instructions in the code. The processor is also configured to insert a protection barrier instruction into the code based at least in part on identifying the one or more unsafe instructions, and translate the code, responsive to inserting the protection barrier instruction. Also provided are embodiments for a computer-implemented method and a computer program product for generating executable code with protection barrier instructions.

Abstract: Calling a function may include: determining whether a call is a direct or an indirect call. In response to determining that the call is an indirect call, a first address stored in a function pointer may be obtained, wherein the function pointer is stored at a first address in a stack frame of a calling function. Whether to execute a nested function call code sequence may be determined based on whether a tag bit in the first address stored in the function pointer is set. In response to determining that the tag bit in the first address is set, a second address stored at a nested function address location may be obtained, wherein the nested function address location is at the first address, and control may be transferred to a called function, wherein the called function is stored at the second address.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector instructions by eliminating one or more vector element reverse operations. The compiler can generate code that includes multiple vector element reverse operations that are inserted by the compiler to account for a mismatch between the endian bias of the instruction and the endian preference indicated by the programmer or programming environment. The compiler then analyzes the code and reduces the number of vector element reverse operations to improve the run-time performance of the code.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector instructions by eliminating one or more vector element reverse operations. The compiler can generate code that includes multiple vector element reverse operations that are inserted by the compiler to account for a mismatch between the endian bias of the instruction and the endian preference indicated by the programmer or programming environment. The compiler then analyzes the code and reduces the number of vector element reverse operations to improve the run-time performance of the code.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector instructions by eliminating one or more vector element reverse operations. The compiler can generate code that includes multiple vector element reverse operations that are inserted by the compiler to account for a mismatch between the endian bias of the instruction and the endian preference indicated by the programmer or programming environment. The compiler then analyzes the code and reduces the number of vector element reverse operations to improve the run-time performance of the code.

Abstract: An optimizing compiler includes a vector optimization mechanism that optimizes vector instructions by eliminating one or more vector element reverse operations. The compiler can generate code that includes multiple vector element reverse operations that are inserted by the compiler to account for a mismatch between the endian bias of the instruction and the endian preference indicated by the programmer or programming environment. The compiler then analyzes the code and reduces the number of vector element reverse operations to improve the run-time performance of the code.

Abstract: A method for improving compile speed in irreducible code regions within a computer program is disclosed. The method comprises determining which of a plurality of code regions within a computer program is irreducible, determining an influence of the irreducible code on blocks within code regions, determining a direction of processing based on the influence of the irreducible code on adjacent blocks and performing a processing based on a current direction of processing and the determined direction of processing.

Abstract: An improved method, apparatus, and computer instructions for generating instructions to process multiple similar expressions. Parameters are identified for the expressions in the original instructions, to form a set of identified parameters typically including the operations performed, the types of data used, and the data sizes. Each type of execution unit that can execute the instructions needed to process the expressions using the set of identified parameters is identified, wherein a set of identified execution unit types is formed. An execution unit type from the set of identified execution unit types is selected to meet a performance goal. The new instructions are generated for the selected execution unit type to process the expressions, and the original instructions for the expressions are discarded.

Abstract: A method, apparatus, and computer instructions for processing instructions. A data dependency graph is built. The data dependency graph is analyzed for recurrences, and unpipelined instructions that lie outside of the recurrences are expanded.

Abstract: An apparatus and method for removing stores to local variables that are not aliased by other variables or to variables which have already been removed by previous optimizations prior to performing dead store elimination optimization are provided. With the method and apparatus, instructions that include a memory reference to a local variable that is not modified by other instructions are identified. For these instructions, an identifier of the variable referenced is maintained in a data structure along with the location of the store instruction in the procedure (for a store instruction) or a load indicator (for a load instruction). The data structure is then traversed to see if there are any store instructions referencing a variable that does not have a corresponding load instruction referencing the same variable. Such store instructions are eliminated prior to performing traditional dead store elimination.