Abstract: A method of and apparatus for efficiently scheduling multiple instruction processors. The instruction processors are assigned to one of a plurality of clusters, such that the system ideally contains a plurality of clusters each having a plurality of instruction processors. Each cluster has a separate scheduling queue wherein the tasks for any one cluster have been selected to maximize cache memory hits by affinity scheduling. Instruction processors are scheduled from the scheduling queue associated with its assigned cluster whenever tasks remain within the cluster. Therefore, under normal system loading conditions, true affinity scheduling is accomplished providing maximum execution efficiency. However, whenever an instruction processor requests assignment and the associated cluster scheduling queue is empty, the instruction processor requests assignment of a task from another scheduling queue associated with a different cluster.