Abstract: Some embodiments of the present invention provide a system that includes a first hard disk drive (HDD) and a second HDD. Within this system, the first HDD is coupled to the second HDD in a non-parallel configuration, which reduces rotational vibration transmitted between the first HDD and the second HDD.

Abstract: Some embodiments of the present invention provide a system that includes a first hard disk drive (HDD) and a second HDD. Within this system, the first HDD is coupled to the second HDD in a non-parallel configuration, which reduces rotational vibration transmitted between the first HDD and the second HDD.

Abstract: Embodiments of the present invention provide a system for preventing dust-fouling in a computer system. During operation of the computer system, the system monitors the computer system and determines if the computer system is becoming dust-fouled. If so, the system reverses fans in the computer system to circulate air through the computer system in the opposite direction to dislodge and disperse dust from the computer system.

Abstract: A random access memory includes a first memory bank, a second memory bank, an error checking circuit operatively connected to receive data read from the first memory bank, and a multiplexer operatively connected to input data read from both the first memory bank and the second memory bank, wherein input selection of the multiplexer is controlled by an output of the error checking circuit. A method for reducing errors in a memory system includes writing data into first and second memory banks of the memory system in parallel, reading data from a desired location of the first memory bank, checking the data read from the first memory bank for errors, if no errors are present, outputting the data read from the first memory bank to a bus, and if the data read from the first memory bank contains errors, outputting data read from a parallel location in the second memory bank to the bus.

Abstract: A random access memory includes a first memory bank, a second memory bank, an error checking circuit operatively connected to receive data read from the first memory bank, and a multiplexer operatively connected to input data read from both the first memory bank and the second memory bank, wherein input selection of the multiplexer is controlled by an output of the error checking circuit. A method for reducing errors in a memory system includes writing data into first and second memory banks of the memory system in parallel, reading data from a desired location of the first memory bank, checking the data read from the first memory bank for errors, if no errors are present, outputting the data read from the first memory bank to a bus, and if the data read from the first memory bank contains errors, outputting data read from a parallel location in the second memory bank to the bus.

Abstract: A current mode logic circuit which is implemented with metal-semiconductor field effect transistors (MESFETs) has a triggering circuit which produces hysteresis in the output of the circuit. That is, the output switches abruptly after the input has almost completed a corresponding transition from one logical output to another in a manner characteristic of triggering circuits such as Schmidt triggers. A triggering voltage is generated in response to one of two complementary outputs by triggering transistors configured as a current switch. The triggering voltage delays switching of a logic switching circuit which produces the two outputs which are a logical or boolean function of the input or inputs. The MESFETs are implemented in gallium arsenide technologies and output is equal to the inverted input.

Abstract: A semiconductor buffer circuit and buffering method for driving capacitive loads that enhances the current sinking and sourcing drive characteristics at times when the input signal is changing. Two transistors are used, a source follower and a current source pull-down, with an input signal applied to the control input of the source follower transistor. The complement of the input signal is capacitively coupled to the control input of the current source pull-down transistor. As a result, changes in the input voltage increase or decrease the conductivity of the current source pull-down transistor, thereby allowing the capacitive load to be charged and discharged more efficiently.

Abstract: A self-timed random access memory circuit is designed on a single monolithic integrated circuit chip. The chip includes a random access memory including addressable storage locations, address decoding circuitry, data input and output circuitry and write enable circuitry. In addition, the chip includes input latches connected to chip input terminals which store data, address and operation control signals from off-chip circuitry in response to a timing signal, also from the off-chip circuitry. Also in response to the timing signal, an output latch on the chip stores data from the random access memory for transmission to output terminals, where the data is available to the off-chip circuitry. The input and output latches permit the self-timed random access memory circuit to perform in a pipelined manner.

Abstract: Circuits and methods for eliminating hold time violations are disclosed. A DE-type flip-flop latches a data input signal on a data input terminal a fraction of a clock period before a triggering edge of the clock signal. The DE-type flip-flop provides a data output signal for a full clock period beginning after the triggering edge of the clock signal. The DE-type flip-flop includes a latch having its data output terminal coupled to the data input terminal of a flip-flop. The flip-flop clock input pin and the latch enable terminal of the latch are connected to a clock line. The DE-type flip-flop used in place of a standard flip-flop, in which a hold time violation occurs, eliminates the hold time violation.