Abstract: A method and testing circuit are provided for tracking transistor stress degradation. A first array of P-channel field effect transistors (PFETs) is connected in parallel. The first array of PFETs is stressed by applying a low gate input and a high source and a high drain to the PFETs during a stress period. The first array of PFETs is tested by operating the PFETs in a saturated region during a test period. A reference array of PFETs is not stressed during the stress period. The reference array of PFETs is activated for testing to compare a saturated drain current performance with the first array of PFETs during the test period.

Abstract: A method for forming a silicon on insulator region on a single crystal silicon substrate, comprising the steps of: forming a first dielectric region in a silicon substrate by etching, deposition, and chemical-mechanical polishing; forming a single crystal layer on the substrate by polysilicon deposition and re-growth or epitaxial growth; removing portions of the single crystal layer to produce silicon islands that are fully on the first dielectric region; and filling in the spaces between the silicon islands with a second dielectric, by deposition and chemical-mechanical-polish, that overlaps peripheral portions of the first dielectric. Additional steps subdivide the fully isolated silicon on insulator regions by etching trenches in the islands and backfilling with a third dielectric, by deposition and chemical-mechanical-polish.

Abstract: A method for forming a silicon on insulator region on a single crystal silicon substrate, comprising the steps of: forming a first dielectric region in a silicon substrate by etching, deposition, and chemical-mechanical polishing; forming a single crystal layer on the substrate by polysilicon deposition and re-growth or epitaxial grownth; removing portions of the single crystal layer to produce silicon islands that are fully on the first dielectric region; and filling in the spaces between the silicon islands with a second dielectric, by deposition and chemical-mechanical-polish, that overlaps peripheral portions of the first dielectric. Additional steps sub-divide the fully isolated silicon on insulator regions by etching trenches in the islands and backfilling with a third dielectric, by deposition and chemical-mechanical-polish.

Abstract: According to the present invention, an improved method for locating particle contamination during the integrated circuit manufacturing process is disclosed. The integrated circuit wafer is grounded and then exposed to an electron beam to create an enhanced electrical potential in any conducting or semi-conducting particles embedded in the layered wafer. The embedded particle will begin to accumulate an electrical charge and will reach a certain electrical potential based on the size and composition of the particle as well as the length of exposure to the electron beam. After a sufficient charge has been accumulated in the embedded particle, the wafer is subjected to burn-in testing. Since the particles embedded in the wafer have been previously exposed to the electron beam, the standard voltages applied during burn-in testing will force a certain number of embedded particles to suffer accelerated breakdown.