Abstract: A multi-mainframe system problem determination method includes receiving, in a first computing system, a data collection trigger, coordinating, in the first computing system, synchronized diagnostic data collection with a second computing system, and delivering the diagnostic data to a storage medium.

Abstract: A multi-mainframe system problem determination method includes recording, in a first computing system, diagnostic data, receiving, in the first computing system, a data collection trigger, responsive to the data collection trigger, coordinating, in the first computing system, synchronized collection of recorded diagnostic data with a second computing system and delivering collected diagnostic data to a storage medium.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: A multi-mainframe operating system serialization method can include receiving, in a first computing system, a request to access a data set on behalf of a first peer application, sending, in the first computing system, a notification to a second peer application to obtain a normal enqueue, in response to the second peer application obtaining the normal enqueue, obtaining, in the first computing system, a first rider enqueue for the data set and sending, in the first computing system, a communication to peer instances to obtain additional rider enqueues for the data set, the additional rider enqueues corresponding to the first rider enqueue.

Abstract: A heterogeneous computing system includes a first server module having a first operating system, a second server module communicatively coupled to the first server module, the second server module having a second operating system dissimilar to the first operating system, a data set accessible by the first server module and the second server module; and a process residing on the first server module, the process configured to grant access to the second server module, from the first server module, to the data set.

Abstract: A multi-mainframe system problem determination method includes receiving, in a first computing system, a data collection trigger, coordinating, in the first computing system, synchronized diagnostic data collection with a second computing system, and delivering the diagnostic data to a storage medium.

Abstract: A multi-mainframe system problem determination method includes recording, in a first computing system, diagnostic data, receiving, in the first computing system, a data collection trigger, responsive to the data collection trigger, coordinating, in the first computing system, synchronized collection of recorded diagnostic data with a second computing system and delivering collected diagnostic data to a storage medium.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: In one embodiment, a system includes at least one outgoing transmission engine implemented in hardware, wherein the at least one outgoing transmission engine is for transmitting data in the plurality of buffers queued to the at least one outgoing transmission engine to the intersystem transmission medium, and a memory for storing the plurality of buffers, wherein each of the buffers queued to the at least one outgoing transmission engine is dequeued after the data is transmitted therefrom and requeued to an available buffer queue. In another embodiment, a system includes the above, except that it includes one or more incoming reception engines instead of outgoing transmission engines. In another embodiment, a method includes buffering data to be sent out by executing a loop of commands on an intersystem communication device and disconnecting the buffers after data has been transferred.

Abstract: A multi-mainframe operating system serialization method can include receiving, in a first computing system, a request to access a data set on behalf of a first peer application, sending, in the first computing system, a notification to a second peer application to obtain a normal enqueue, in response to the second peer application obtaining the normal enqueue, obtaining, in the first computing system, a first rider enqueue for the data set and sending, in the first computing system, a communication to peer instances to obtain additional rider enqueues for the data set, the additional rider enqueues corresponding to the first rider enqueue.

Abstract: A heterogeneous computing system includes a first server module having a first operating system, a second server module communicatively coupled to the first server module, the second server module having a second operating system dissimilar to the first operating system, a data set accessible by the first server module and the second server module; and a process residing on the first server module, the process configured to grant access to the second server module, from the first server module, to the data set.

Abstract: A method and system for a decentralized distributed storage data system. A plurality of central processors each having a cache may be directly coupled to a shared set of data storage units. A high speed network may be used to communicate at a physical level between the central processors. A coherency protocol may be used to communicate at a logical level between the central processors.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: In one embodiment, a system includes at least one outgoing transmission engine implemented in hardware, wherein the at least one outgoing transmission engine is for transmitting data in the plurality of buffers queued to the at least one outgoing transmission engine to the intersystem transmission medium, and a memory for storing the plurality of buffers, wherein each of the buffers queued to the at least one outgoing transmission engine is dequeued after the data is transmitted therefrom and requeued to an available buffer queue. In another embodiment, a system includes the above, except that it includes one or more incoming reception engines instead of outgoing transmission engines. In another embodiment, a method includes buffering data to be sent out by executing a loop of commands on an intersystem communication device and disconnecting the buffers after data has been transferred.

Abstract: A device that synchronizes circuits over asynchronous links is disclosed. Some embodiments of the invention include a device that comprises a plurality of circuits. One of the plurality of circuits is designated as a “master” circuit. The master circuit is configured to send a first synchronization signal to one or more of the plurality of circuits, and each circuit that receives the first synchronization signal is configured to responsively send a second synchronization signal to one or more of the plurality of circuits.

Abstract: A switch comprising front-end and back-end application specific integrated circuits (ASICs) is disclosed. Frame storage and retrieval in the switch is achieved by dividing a frame into equal sized portions that are sequentially stored in switch memory during an assigned time slot. Control logic coupled to the front-end and back-end ASICs assigns the time slot either dynamically or statically.

Abstract: A link level flow control technique implements a “pull frame” transmission model in a Fibre Channel network. In one embodiment, frames remain in a first Fibre Channel device until they are requested by a second Fibre Channel device, wherein the second Fibre Channel device does not issue a request unless conditions are such that it can immediately transmit the frame toward its target destination. In another embodiment, a Fibre Channel device provides hardware messaging capability to support the pull model. In yet another embodiment, multiple Fibre Channel devices in accordance with the invention may be coupled to provide high port-count Fibre Channel switches.