Abstract: An on-line adaptive distributed diagnostic method for use in an arbitrary network comprised of N nodes, where N is greater than or equal to 3. The algorithms of the present invention provide on-line diagnosis in the presence of node and link failure. In the network, each node is capable of executing an algorithm used in the diagnostic method to update a packet which communicates between network nodes.

Abstract: The present invention pertains to a packet switch. The packet switch is comprised of a global shared-memory queue having M storage addresses in which respective packets are stored, where M.gtoreq.3 and is an integer. The packet switch is also comprised of a presentation network having N input ports for receiving packets and providing the respective packets to desired addresses in the queue, where N.ltoreq.3 and is an integer. The queue is in communication with the presentation network for receiving the packets. The packet switch is also comprised of a distribution network having J input ports, where J.ltoreq.1, for receiving packets from the queue and providing them to the desired output ports. The distribution network is in communication with the queue. There is also means for ordering packets received by the presentation network such that packets received sequentially by the presentation network are caused to be provided by the presentation network to consecutive addresses in the queue.

Abstract: An adaptive distributed system and method for fault tolerance. The system is comprised of a network including N nodes, where N is an integer greater than or equal to 3 and each node is able to execute an algorithm in communication with the network. Each of the N nodes is in communication with at least one other node by way of the network. In addition, each node has a device for testing whether a node is in a desired state or an undesired state and for choosing which node to test based on given circumstances at a corresponding time. The method comprises the steps of using a tester node to choose and test another node to determine whether the other node is in a desired state or undesired state. Thereafter, if the node being tested is in a desired state, the tester node transmits an activation signal to the tested node to cause same to become the next tester node. These steps are then repeated on at least one other node at another predetermined location until a processor in a desired state is tested.

Abstract: The present invention pertains to a packet switch. The packet switch is comprised of a global shared-memory queue having M storage addresses in which respective packets are stored, where M.gtoreq.3 and is an integer. The packet switch is also comprised of a presentation network having N input ports for receiving packets and providing the respective packets to desired addresses in the queue, where N.gtoreq.3 and is an integer. The queue is in communication with the presentation network for receiving the packets. The packet switch is also comprised of a distribution network having J input ports, where J.gtoreq.1, for receiving packets from the queue and providing them to the desired output ports. The distribution network is in communication with the queue. There is also means for ordering packets received by the presentation network such that packets received sequentially by the presentation network are caused to be provided by the presentation network to consecutive addresses in the queue.