Patents by Inventor Ronald Patrick
Ronald Patrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11995678Abstract: Methods, systems and device for verifying a transaction in a loyalty or advertising system are described. One such method includes: receiving, at least one processor, transaction data associated with a transaction between a customer and a merchant; determining, at the at least one processor, from the transaction data whether the customer and the merchant are associated with the loyalty or advertising system; and upon determining from the transaction data whether the transaction corresponds to a reward or advertisement, triggering the redemption of the reward or advertisement.Type: GrantFiled: May 18, 2022Date of Patent: May 28, 2024Assignee: EDATANETWORKS INCInventors: Terrance Patrick Tietzen, Matthew Arnold Macpherson Bates, Ronald Rog
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Publication number: 20240170452Abstract: Methods for substrate processing include attaching a plurality of dies to a first carrier, wherein each die has a first side and a second side opposite the first side, wherein the first side is attached to the first carrier and wherein the plurality of dies are spaced horizontally from one another on the first carrier; filling spaces between the plurality of dies and covering the second sides of the plurality of dies with a dielectric or metal; grinding or polishing the dielectric or metal covering the second sides and grinding or polishing the second sides until the second sides are exposed and the plurality of dies have a substantially uniform thickness; and after grinding or polishing, dishing die faces of the plurality of dies to a desired dishing profile.Type: ApplicationFiled: November 22, 2022Publication date: May 23, 2024Inventors: Anup PANCHOLI, Marvin Louis BERNT, Vincent DICAPRIO, Ronald Patrick HUEMOELLER
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Publication number: 20240158356Abstract: Compounds and methods for treating diseases mediated by a P2X3 and/or a P2X2/3 receptor antagonist, the methods comprising administering to a subject in need thereof an effective amount of a compound of formula (I): or a pharmaceutically acceptable salt, solvate or prodrug thereof, wherein X is O, D, Y, R1, R2, R3, R4, R5, R6, R7 and R8 are as defined herein.Type: ApplicationFiled: April 27, 2023Publication date: May 16, 2024Applicant: Roche Palo Alto LLCInventors: CHRIS ALLEN BROKA, DAVID SCOTT CARTER, MICHAEL PATRICK DILLON, RONALD CHARLES HAWLEY, ALAM JAHANGIR, CLARA JEOU JEN LIN, DANIEL WARREN PARISH
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Publication number: 20240137239Abstract: An application server may receive, via a user interface of a cloud-based data management platform storing a set of data objects, a user input to generate a communication channel of a group-based communication platform that is separate from the cloud-based data management platform. In some examples, the communication channel may be for a data object of the plurality of data objects. The application server may then retrieve a group of users that are linked to the data object within the cloud-based data management platform and display a list of options for generating the communication channel. The list of options may include the group of users for including in the communication channel, a privacy level for the communication channel, and an identifier of the communication channel.Type: ApplicationFiled: October 31, 2023Publication date: April 25, 2024Inventors: Michael Patrick McGinty, Ronald Jay Hemphill, Sreejesh Divakaran Nair
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Patent number: 11901335Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.Type: GrantFiled: March 29, 2022Date of Patent: February 13, 2024Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Michael Kelly, Ronald Patrick Huemoeller, David Jon Hiner
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Publication number: 20240021571Abstract: Methods for bonding semiconductor surfaces leverage hybrid bonding processes to enable heterogeneous integration architectures. In some embodiments, the methods may comprise forming a semiconductor structure on a silicon-based substrate with a first set of exposed conductive connections on a top surface of the semiconductor structure. The first set of exposed conductive connections having a pitch of less than approximately 10 microns. Forming an advanced rectangular substrate panel with a second set of exposed conductive connections. The second set of exposed conductive connections having a pitch of less than approximately 10 microns. Bonding a top surface of the semiconductor structure to a top surface of the advanced rectangular substrate panel using a hybrid bonding process to bond the semiconductor structure to the advanced rectangular substrate panel.Type: ApplicationFiled: July 18, 2022Publication date: January 18, 2024Inventors: Anup PANCHOLI, Marvin Louis BERNT, Ronald Patrick HUEMOELLER, Avinash SHANTARAM, Vincent DICAPRIO
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Publication number: 20240009955Abstract: A protective cover includes a composite sheet including a substrate formed from a nonwoven material. The substrate has a first surface and an opposite second surface, and a first layer of plastic film is adjacent the substrate first surface. The protective cover also includes a first end, a second end, a first lateral edge extending between the first and the second end, a second lateral edge extending between the first end and the second end, and an axis extending between the first lateral edge and the second lateral edge. The composite sheet is folded about the axis and the first end of the composite sheet is proximate the second end of the composite sheet. The protective cover also includes a partially enclosed space having an opening proximate the first and second ends of the composite sheet, and the first layer of plastic film is within the partially enclosed space.Type: ApplicationFiled: September 22, 2023Publication date: January 11, 2024Inventor: Ronald Patrick Weir
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Patent number: 11848214Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.Type: GrantFiled: July 27, 2021Date of Patent: December 19, 2023Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner
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Patent number: 11787146Abstract: Methods of making a protective cover. According to one method, a composite sheet is formed by providing a substrate formed from a nonwoven material having a puncture resistance exceeding 500 N, the substrate having a first surface and a second surface, disposing a first layer of plastic film on the substrate first surface and a second layer of plastic film on the substrate second surface. The composite sheet has a first end, a second end, a first lateral edge, a second lateral edge, and an axis extending between the first lateral edge and the second lateral edge. The method also includes folding the composite sheet about the axis to bring the first end of the composite sheet proximate the second end of the composite sheet and define a partially enclosed space having an opening proximate the first and second ends of the composite sheet.Type: GrantFiled: August 3, 2020Date of Patent: October 17, 2023Assignee: Industrial Packaging Supplies, Inc.Inventor: Ronald Patrick Weir
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Publication number: 20230040553Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die.Type: ApplicationFiled: August 19, 2022Publication date: February 9, 2023Inventors: Michael G. Kelly, Ronald Patrick Huemoeller, Won Chul Do, David Jon Hiner
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Publication number: 20230021530Abstract: A timeline generation and solving tool is provided to parameterize a project at an application lifecycle management (“ALM”) tool, and generate and solve a timeline of features according to the parameterized project. The Scrum master may re-parameterize the project, causing a new timeline to be generated, solved, and visualized. In this fashion, the Scrum master may rapidly prototype many project parameterizations, resulting in many possible timelines. Without the use of a timeline generation and solving tool which interfaces with an ALM tool, retrieves project features, and converts project features to a common format suitable for computations based on working speeds, a Scrum master would need to generate and check a timeline by hand, and work indirectly by manually copying data out of the ALM tool, leading to a slow and potentially error-prone project roadmapping process which does not permit rapid prototyping of possible timelines.Type: ApplicationFiled: July 22, 2022Publication date: January 26, 2023Inventors: Wesley Mao, Stephen Richard Jones, Daniel Joseph Sanders, Milo Harper Skalicky, Ronald Patrick Allen, Sarah Lynn Richards, Kevin Michael Arnold
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Patent number: 11555336Abstract: A powered latch system for motor vehicles includes at least one powered latch that can be controlled based, at least in part, on vehicle operating conditions. The system may be configured to control unlatching of the vehicle doors utilizing data relating to the vehicle speed and/or the existence of a crash event. The powered latch system can be configured as required for various vehicles, and to accommodate specific operating requirements with respect to child locks in various geographic jurisdictions.Type: GrantFiled: April 29, 2019Date of Patent: January 17, 2023Assignee: Ford Global Technologies, LLCInventors: Robert Bruce Kleve, John Thomas Ricks, Jim Michael Weinfurther, John Robert Van Wiemeersch, Ronald Patrick Brombach, Laura Viviana Hazebrouck, Lisa Therese Boran, Howard Paul Tsvi Linden
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Patent number: 11545405Abstract: A fingerprint sensor package, including a sensing side for sensing fingerprint information and a separate connection side for electrically connecting the fingerprint sensor package to a host device, is disclosed. The fingerprint sensor package can also include a sensor integrated circuit facing the sensing side and substantially surrounded by a fill material. The fill material includes vias at peripheral locations around the sensor integrated circuit. The fingerprint sensor package can further include a redistribution layer on the sensing side which redistributes connections of the sensor integrated circuit to the vias. The connections can further be directed through the vias to a ball grid array on the connection side. Some aspects also include electrostatic discharge traces positioned at least partially around a perimeter of the connection side. Methods of manufacturing are also disclosed.Type: GrantFiled: April 24, 2020Date of Patent: January 3, 2023Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Ronald Patrick Huemoeller, David Bolognia, Robert Francis Darveaux, Brett Arnold Dunlap
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Publication number: 20220347076Abstract: Provided are hair treatment compositions comprising one or more polysaccharides and their use in improving hair strength.Type: ApplicationFiled: October 5, 2020Publication date: November 3, 2022Inventors: Lauren A. Trahan, Elizabeth May Patel, Ronald Patrick McLaughlin, Joseph Muscat, Andrew R. Avery
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Patent number: 11466484Abstract: A latch system for vehicle doors includes a powered latch including a powered actuator that is configured to unlatch the powered latch. An interior unlatch input feature such as an unlatch switch can be actuated by a user to provide an unlatch request. The system may include a controller that is operably connected to the powered actuator of the powered latch. The controller is configured such that it does not unlatch the powered latch if a vehicle speed is greater than a predefined value unless the interior latch feature is actuated at least two times according to predefined criteria.Type: GrantFiled: September 24, 2018Date of Patent: October 11, 2022Assignee: Ford Global Technologies, LLCInventors: H. Paul Tsvi Linden, Daniel Carl Bejune, John Robert Van Wiemeersch, Kosta Papanikolaou, Noah Barlow Mass, Lisa Therese Boran, Ronald Patrick Brombach, Jim Michael Weinfurther, Robert Bruce Kleve, John Thomas Ricks
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Patent number: 11424155Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die.Type: GrantFiled: July 10, 2020Date of Patent: August 23, 2022Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Michael G. Kelly, Ronald Patrick Huemoeller, Won Chul Do, David Jon Hiner
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Publication number: 20220223563Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Inventors: Michael Kelly, Ronald Patrick Huemoeller, David Jon Hiner
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Patent number: 11289451Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.Type: GrantFiled: June 2, 2020Date of Patent: March 29, 2022Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Michael Kelly, Ronald Patrick Huemoeller, David Jon Hiner
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Publication number: 20210358770Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.Type: ApplicationFiled: July 27, 2021Publication date: November 18, 2021Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner
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Publication number: 20210296139Abstract: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Ronald Patrick Huemoeller, Michael G. Kelly, Curtis Zwenger