Abstract: Various techniques are disclosed for offloading the processing of data packets that contain financial market data. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize financial market data in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

Abstract: Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

Abstract: Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.

Abstract: Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

Abstract: Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.

Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.

Abstract: A multi-functional data processing pipeline is disclosed where the multi-functional pipeline comprises a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations. The multi-functional pipeline can be configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline. In example embodiments, the pipelined data processing engines can include correlation logic, and such pipelines can be used to accelerate convolutional layers in machine-learning technology such as convolutional neural networks.

Abstract: Disclosed herein is a method and apparatus for hardware-accelerating various data quality checking operations. Incoming data streams can be processed with respect to a plurality of data quality check operations using offload engines (e.g., reconfigurable logic such as field programmable gate arrays (FPGAs)). Accelerated data quality checking can be highly advantageous for use in connection with Extract, Transfer, and Load (ETL) systems.

Abstract: Disclosed herein are methods and systems for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. In accordance with exemplary embodiments, the generation of classification information about unstructured data can be hardware-accelerated by processing streaming unstructured data through a reconfigurable logic device, a graphics processor unit (GPU), or chip multi-processor (CMP) to generate the classification metadata about the unstructured data.

Abstract: Disclosed herein is a method and system for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. In accordance with exemplary embodiments, the generation of metadata indexes about unstructured data can be hardware-accelerated by processing streaming unstructured data through a reconfigurable logic device to generate the metadata about the unstructured data for the index.

Abstract: An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. An embodiment of the integrated circuit includes a run-time scalable block cipher circuit, wherein the run-time scalable block cipher circuit is run-time scalable to balance throughput with power consumption.

Abstract: Disclosed herein is a method and system for accelerating the generation of pattern indexes. In exemplary embodiments, regular expression pattern matching can be performed at high speeds on data to determine whether a pattern is present in the data. Pattern indexes can then be built based on the results of such regular expression pattern matching. Reconfigurable logic such a field programmable gate arrays (FPGAs) can be used to hardware accelerate these operations.

Abstract: Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.

Abstract: A re-configurable logic device such as a field programmable gate array (FPGA) can be used to deploy a data processing pipeline, the pipeline comprising a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations, wherein the pipeline comprises a multi-functional pipeline, and wherein the re-configurable logic device is further configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline.

Abstract: Methods and apparatuses for processing streaming data using programmable logic are disclosed. With an exemplary embodiment, a programmable logic device can be used to sort streaming data and provide a processor with access to the sorted data. With another exemplary embodiment, an Internet search engine can include a programmable logic device to perform match operations in response to search queries for web pages. With another exemplary embodiment, a programmable logic device is configured to perform match operations on streaming data while a processor is freed to perform other tasks.

Abstract: An encryption technique is disclosed for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride. A corresponding decryption technique is also disclosed.

Abstract: An encryption technique is disclosed for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride. A corresponding decryption technique is also disclosed.

Abstract: Disclosed herein is a method and system for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. In accordance with exemplary embodiments, the generation of metadata indexes about unstructured data can be hardware-accelerated by processing streaming unstructured data through a reconfigurable logic device to generate the metadata about the unstructured data for the index.

Abstract: An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. An embodiment of the integrated circuit includes a run-time scalable block cipher circuit, wherein the run-time scalable block cipher circuit is run-time scalable to balance throughput with power consumption.

Abstract: Disclosed herein is a method and system for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. In accordance with exemplary embodiments, the generation of metadata indexes about unstructured data can be hardware-accelerated by processing streaming unstructured data through a reconfigurable logic device to generate the metadata about the unstructured data for the index.