Abstract: For use in an x86-compatible processor capable of executing MMX.TM. instructions calling for partitioned data to be shifted or routed, an integrated routing and shifting circuit, a method of operation and a computer system containing the same. In one embodiment, the circuit includes: (1) a lower shifter that receives partitioned data therein and shifts at least a first portion of the partitioned data as a function of a received control signal and (2) an upper shifter/router, coupled to the lower shifter and having partitioned input lines and partitioned output lines, that receives the partitioned data from the lower shifter into the source register and selectively shifts or routes at least a second portion of the partitioned data as a function of the received control signal while transferring the partitioned data from the partitioned input lines to the partitioned output lines.

Abstract: A processor architecture and methodology for executing a condition dependent instruction over a plurality of execution stages in a microprocessor. The microprocessor includes a memory for storing microinstructions. The method involves various steps. In one step, an instruction is received. In another step, a first microinstruction is issued from the memory. This first microinstruction comprises a control and a base address. In yet another step, a secondary address is determined, external from the memory, by evaluating a plurality of predetermined data. In a still another step, the base address and the secondary address are combined to form a destination address in response to the control signal, wherein the destination address identifies a second microinstruction in the memory to execute a successive stage for the received instruction.