Abstract: A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package.

Abstract: A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package.

Abstract: A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package.

Abstract: Methods are disclosed for singulating block-molded IC packages. The methods of the invention include steps for making a partial cut in a block-molded semiconductor array, the partial cut defining the perimeter of an IC package and extending partially through the thickness of the array material. In a subsequent step, a final cut is made in alignment with the partial cut at the perimeter of the package such that the package is severed from adjacent material. Various embodiments of the invention are disclosed, including methods for making a plurality of partial cuts prior to making the final cut severing the package from the array, making cuts approaching from the same surface of the array, and making cuts approaching from opposing surfaces of the array. The partial cutting steps are used to prevent array warpage and facilitate hold-down during ball attach and/or singulation processes.