Abstract: A sub-circuit of a voltage regulator includes a load condition detection circuit and a controllable circuit. The load condition detection circuit is arranged to detect a load transient frequency of a load powered by the voltage regulator, and generate a control signal according to a detection result of the load transient frequency. The controllable circuit is arranged to receive the control signal, wherein an operational behavior of the controllable circuit dynamically changes in response to the control signal.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a first liquid crystal panel for displaying a picture, a second liquid crystal panel for switching between a privacy mode and a sharing mode, and a back light assembly for emitting light; the second liquid crystal panel is disposed on a light-emitting side of the back light assembly; the first liquid crystal panel is disposed on a side of the second liquid crystal panel away from the back light assembly, and a spacer film is disposed between the first liquid crystal panel and the second liquid crystal panel, and is attached to the second liquid crystal panel.

Abstract: A system for determining the cause of an abnormality in a semiconductor manufacturing process includes an abnormality mode determination module, a selection module, and a root cause analysis module. The abnormality mode determination module is used to determine the similarity between wafer bin maps containing the abnormal data. When the similarity among the wafer maps is higher than a reference value, the selection module executes the steps of: determining a bad lot based on the wafer maps where the similarity is higher than the reference value; determining a time span within which the bad lot is generated; selecting other bad lots occurring in the time span and satisfying a failure model; selecting a good lot based on a fixed lot interval. The root cause analysis module is used to execute the steps of calculating the correlation among data to obtain confidence indexes.

Abstract: A processing method for automatically generating machining features is provided. A workpiece CAD file is obtained to perform a CAD numerical analysis on a blank body. With the workpiece CAD file being used as a target, a workpiece CAD appearance is compared with the blank body to obtain a feature identification result of a first to-be-processed blank body, which includes identifying data of a to-be-removed blank body and a feature of a first processing surface. A geometric analysis is performed on the first processing surface feature and a tool selection range is determined. A virtual cutting simulation is performed on the first processing surface to generate a processed area data and an unprocessed area data. A spatial coordinate mapping comparison between the unprocessed area data and a surface data of the workpiece CAD file is performed to obtain a feature identification result of a second to-be-processed blank body.

Abstract: An image calibration method for use in an imaging system. The imaging system includes a projection device, a color detector and a processor. The image calibration method includes in an ambient light environment, the color detector taking a background luminance and an ambient measurement of a test image on a projection surface, and the processor generating a color appearance representation using the background luminance and the ambient measurement, in a darkroom environment, the color detector taking a darkroom measurement of a test image, and if a surround ratio is less than a predetermined threshold, the processor generating a target using the darkroom measurement and the color appearance representation, and the processor configuring a gamut of the projection device according to the target, and adjusting an image according to the gamut and the darkroom measurement, and the projection device projecting the adjusted image.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure.

Abstract: An echo estimation system includes a transceiver circuitry and a processor circuitry. The processor circuitry is coupled to the transceiver circuitry. The processor circuitry is configured to calculate linear echo power and non-linear echo power based on a signal under test in the transceiver circuitry. The linear echo power and the non-linear echo power are utilized to determine a quality of the transceiver circuitry or utilized to determine component parameters of the transceiver circuitry.

Abstract: A system for determining the cause of an abnormality in a semiconductor manufacturing process includes an abnormality mode determination module, a selection module, and a root cause analysis module. The abnormality mode determination module is used to determine the similarity between wafer bin maps containing the abnormal data. When the similarity among the wafer maps is higher than a reference value, the selection module executes the steps of: determining a bad lot based on the wafer maps where the similarity is higher than the reference value; determining a time span within which the bad lot is generated; selecting other bad lots occurring in the time span and satisfying a failure model; selecting a good lot based on a fixed lot interval. The root cause analysis module is used to execute the steps of calculating the correlation among data to obtain confidence indexes.

Abstract: The present invention describes a transmission system for removing resonance and improves performance by utilizing air bridges connecting ground lines in a G-S-S-G transmission line configuration.

Abstract: A high-bandwidth bend-insensitive multimode fiber includes a core laver and a cladding including an inner cladding, a depressed cladding, and an outer cladding arranged sequentially from inside to outside. The core layer is a silicon dioxide glass layer co-doped with germanium, phosphorus (P), and fluorine (F) and has a refractive index profile in a shape of a parabola, a distribution index in a range of 2.0-2.3, a radius in a range of 23-27 ?m, and a maximum relative refractive index difference in a range of 0.9-1.2% at its center. A contribution amount of P at the center is in a range of 0.01-0.30%. A doping amount of F increases from the center to the edge of the core layer. A contribution amount of F at the center and edge of the core layer is in range of 0.0% to ?0.1%, and ?0.40% to ?0.20%, respectively.

Abstract: Aspects of this disclosure are directed to a voice message display method and apparatus in an application, a computer device, and a computer-readable storage medium. The method can be performed by a terminal on which an application is installed and is capable of receiving a voice message. The method can include starting an application, and obtaining n voice messages published by at least one user account. The method can further include displaying a voice message presentation interface of the application, where the voice message presentation interface displays the voice message in a virtual world and the voice message are displayed by using a visible element in the virtual world as a carrier.

Abstract: A method for adjusting uniformity of image color tones includes setting brightness of a darkest display region as target brightness and setting color temperature coordinates of a designated display region as target color temperature coordinates of at least one part of display regions of a display, comparing the brightness and the color temperature coordinates of each display region of the at least one part of display regions with the target brightness and the target color temperature coordinates for generating a first calibrated color tone, generating a second calibrated color tone of the each display region of the at least one part of display regions according to an Alpha channel parameter and the first calibrated color tone, generating a uniformity compensated image layer according to all second calibrated color tones, and virtually overlaying the uniformity compensated image layer on the at least one part of display regions.

Abstract: A magnetic component includes a magnetic core and a first winding module. The magnetic core has two opposite openings and at least one magnetic column. The first winding module has a plurality of annular metal plates disposed around the at least one magnetic column. Each of the annular metal plates has an electrical connection end, an annular portion and a heat-dissipating end. The electrical connection end and the heat-dissipation end are located at the two opposite openings of the magnetic core respectively. A thermal-dissipating area of the heat-dissipating end is greater than a cross-sectional area of a connection portion between the heat-dissipating end and the annular portion.