Abstract: An improved alignment mark used by a laser trimming tool to locate fuses in an underlying integrated circuit is formed using conventional processing sequences. The design features high resolution and improved low noise characteristics. The alignment mark is etched in a shallow layer over a metal layer rather than in the metal itself. The edges which are sensed by the scanning alignment laser of the trimming tool have their elevated portions external to the alignment mark. The improved design replaces a prior art design in which the metal mark protruded from a deep area in the site region. Debris in deep areas adjacent to alignment marks etched in metal, is avoided by the improved design. The absence of this debris virtually eliminates noise in the alignment scan thereby greatly reducing alignment errors.

Abstract: A process for avoiding dishing in a planarizing layer whose final thickness is reduced by Chem. Mech. Polishing, is described. The first step is to coat the surface to be planarized with a layer of a hard dielectric material, such as silicon nitride, prior to depositing the planarizing medium. After the latter has been reflowed, its thickness is reduced by means of CMP. While CMP is being applied, the etch rate is constantly sensed. When the etch front approaches the aforementioned hard layer a decrease in the etch rate is sensed and etching is terminated, thereby eliminating any dishing effects.

Abstract: The memory cell, such as a DRAM, has a crown-shaped capacitor structure and is formed on a substrate having a first conductivity type (i.e., p-type) and preferably has the following structure. Portions of the substrate are doped to have a conductivity type opposite that of the substrate (i.e, n-type) to form drain and source regions. A gate is formed between the drain and source regions having a gate oxide adjacent the substrate, a first polysilicon region (Poly-1), tungsten silicide layer, and an oxide layer and SiyNx, respectively, on the gate oxide. SiyNx spacers cover the sides of the gate regions. Above the oxide layer are tetetraethylorthosilicate (TEOS) and borophosphosilicate (BPSG) layers. A second polysilicon layer (Poly-2) is patterned to form a bitline which contacts the source region. A layer of tungsten silicide, oxide, and SiyNx are formed on top of the bitline. SiyNx spacers surround the bitline. A crown-shaped capacitor contacts the drain region.

Abstract: The present invention is a method of capping with a high compressive stress oxide, a boron phospho-silicate glass (BPSG) interlayer dielectric (ILD) gapfill that has been deposited on a topographic silicon substrate, in order to eliminate the formation of cracks in subsequently deposited silicon nitride (SiN) layers, other subsequently deposited high tensile stress layers and cracks that result from other post-BPSG deposition high temperature processes.

Abstract: A method of manufacturing a monitor pad for measuring the topographic step height for the CMP planarization process is provided. The monitor pad contains an area having step height lower than the worst condition on the wafer. The method comprises the steps of forming a field oxide area; defining area A, area B, and area C on the field oxide area and area B being located between area A and area C; and forming a multiple layers of polysilicon and metal on area A and area C. Consequently, the step height of area B is lower than the worst condition on the wafer. The step height of the monitor pad will be enough to reflect the polish condition on the surface of the wafer after CMP planarization.

Abstract: A process for forming a DRAM capacitor structure, comprised with a HSG silicon/polysilicon crown shaped storage node structure, has been developed. The process features the use of a series of wet clean procedures, used to prepare the surface of the HSG silicon/polysilicon, crown shaped storage node structure, for the formation of an overlying capacitor dielectric layer. A first wet clean procedure is employed after the formation of the crown shaped storage node structure via a CMP procedure, featuring an ammonium hydroxide--hydrogen peroxide solution, used to remove CMP, as well as HSG silicon particles from the surface of a photoresist plug used for definition of the crown shaped storage node structure. Another wet clean procedure, first performed in a DHF solution, then followed by a sulfuric acid--hydrogen peroxide treatment, is used to prepare the HSG silicon/polysilicon, crown shaped storage node structure, for formation of the overlying capacitor dielectric layer.

Abstract: A method for removing from a patterned silicon containing dielectric layer a patterned partially fluorinated photoresist layer employed in patterning the patterned silicon containing dielectric layer. There is first formed over a semiconductor substrate a metal contact layer having a silicon containing dielectric layer formed thereover. There is then formed upon the silicon containing dielectric layer a patterned photoresist layer. There is then formed by use of a reactive ion etch (RIE) plasma etch method employing a fluorine containing etchant a via through the silicon containing dielectric layer to form a patterned silicon containing dielectric layer reaching the metal contact layer.

Abstract: A method of forming cavities in a non-conducting layer on a semiconductor device is provided which can be carried out by first providing a pre-processed semi-conducting substrate which has a non-conducting layer and a patterned photoresist layer sequentially deposited and formed on top, and then conformally depositing a polymeric material layer on top of the non-conducting and the photoresist layer, and then etching the polymeric material layer to form polymeric sidewall spacers on the patterned photoresist layer, and then etching cavities in the non-conducting layer to expose the semi-conducting substrate. The polymeric sidewall spacers formed on the sidewalls of the photoresist openings allow the fabrication of cavities such as contact holes or line spacings of reduced dimensions while utilizing a conventional low cost photolithographic method for patterning.

Abstract: An improved alignment mark used by a laser trimming tool to locate fuses in an underlying integrated circuit is formed using conventional processing sequences. The design features high resolution and improved low noise characteristics. The alignment mark is etched in a shallow layer over a metal layer rather than in the metal itself. The edges which are sensed by the scanning alignment laser of the trimming tool have their elevated portions external to the alignment mark. The improved design replaces a prior art design in which the metal mark protruded from a deep area in the site region. Debris in deep areas adjacent to alignment marks etched in metal, is avoided by the improved design. The absence of this debris virtually eliminates noise in the alignment scan thereby greatly reducing alignment errors.

Abstract: A method for removing from a semiconductor substrate a partially fluorinated photoresist layer. There is first formed upon a semiconductor substrate a partially fluorinated photoresist layer. The partially fluorinated photoresist layer has a fluorinated surface layer of the partially fluorinated photoresist layer and an underlying non-fluorinated remainder layer of the partially fluorinated photoresist layer. The fluorinated surface layer of the partially fluorinated photoresist layer is then removed through a first etch method. The first etch method employs an oxygen containing plasma at a radio frequency power no greater than about 500 watts and a temperature no greater than about 120 degrees centigrade. Finally, the underlying non-fluorinated remainder layer of the partially fluorinated photoresist layer is removed through a second etch method.

Abstract: A one mask/four etch step process to form an curved storage node for an advanced DRAM cell capacitor. A first undoped oxide layer and a second doped oxide layer are formed over associated field effect transistors on the substrate surface. Next, a photoresist pattern having an opening over the node (source) is formed over the second oxide layer. In the first etch step, the second oxide layer is isotropically etched through the opening. The isotropic etch selectively etches the second doped oxide layer thereby forming an arced electrode hole in the second oxide layer. Then in the second etch step, the first oxide layer is anisotropically etched to form the node contact hole. A first conductive layer is formed over resultant surface. A polarization layer is formed covering bottom portions of the first conductive layer but exposing the tops of the first conductive layer. In the third etch step, the exposed tops of the first conductive layer are etched off thereby defining curved bottom storage electrodes.

Abstract: The invention provides a method of forming field oxide regions between active regions in a semiconductor substrate. The invention forms nitride feet on the sidewalls of a nitride oxidation mask to prevent formation of the bird's beak on the field oxide and reduce stress in the active areas. The invention begins by forming a first oxide layer and a masking block, over the active regions. A second nitride layer is deposited over the masking block and the substrate surface. The second nitride layer is anisotropically etched with a customized etch forming nitride spacers on the sidewalls of the masking block, and nitride spacer feet on the surface of the first oxide layer. The customized etch of the invention optimizes the microloading effects to properly form the nitride feet. The substrate is oxidized, using the masking block nitride spacers and the nitride spacer feet as an oxidation mask to form field oxide regions. The nitride feet eliminate bird's beak problem.

Abstract: A new method for forming small contacts and for planarizing the dielectric layer in the fabrication of an integrated circuit device is described. Semiconductor device structures are formed in and on a semiconductor substrate. A dielectric layer is deposited overlying the semiconductor device structures. The dielectric layer is covered with a photoresist mask and partially etched into to form first openings of a first width wherein the first openings do not contact the underlying semiconductor device structures. An oxide layer is deposited over the dielectric layer and within the first openings whereby second openings are formed having a second width smaller than the first width. The oxide layer is etched away whereby the second openings are extended through the dielectric layer to the underlying semiconductor device structures to form small contact openings having the second width and whereby the dielectric layer is planarized.