Patents by Inventor Rongming Chu
Rongming Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9761438Abstract: A semiconductor structure comprising a layer of a III-N material and at least a portion of said layer being covered by a passivation layer, wherein the passivation layer comprises a first layer of SiN formed on said at least a portion of said III-N material layer and a second layer of SiN formed on said first layer of SiN; the first SiN layer having a first thickness and generating tensile stress in the structure and the second SiN layer having a second thickness and generating compressive stress in the structure.Type: GrantFiled: May 8, 2014Date of Patent: September 12, 2017Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Xu Chen
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Patent number: 9691909Abstract: A diode and a method of making same has a cathode an anode and one or more semiconductor layers disposed between the cathode and the anode. A dielectric layer is disposed between at least one of the one or more semiconductor layers and at least one of the cathode or anode, the dielectric layer having one or more openings or trenches formed therein through which the at least one of said cathode or anode projects into the at least one of the one or more semiconductor layers, wherein a ratio of a total surface area of the one or more openings or trenches formed in the dielectric layer at the at least one of the one or more semiconductor layers to a total surface area of the dielectric layer at the at least one of the one or more semiconductor layers is no greater than 0.25.Type: GrantFiled: July 10, 2015Date of Patent: June 27, 2017Assignee: HRL Laboratories, LLCInventor: Rongming Chu
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Publication number: 20170148912Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.Type: ApplicationFiled: November 7, 2016Publication date: May 25, 2017Applicant: HRL Laboratories, LLCInventor: Rongming CHU
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Patent number: 9646839Abstract: A method of forming an Ohmic contact including forming a Ta layer in a contact area of a barrier, forming a Ti layer on the first Ta layer, and forming an Al layer on the Ti layer, wherein the barrier layer comprises AlGaN having a 10% to 40% Al composition and a thickness in a range between 30 ? to 100 ?, and wherein the barrier layer is on a channel layer comprising GaN.Type: GrantFiled: June 11, 2014Date of Patent: May 9, 2017Assignee: HRL Laboratories, LLCInventors: Mary Y. Chen, Rongming Chu
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Publication number: 20170104477Abstract: A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.Type: ApplicationFiled: February 26, 2016Publication date: April 13, 2017Applicant: HRL Laboratories, LLCInventors: Brian HUGHES, Rongming CHU
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Publication number: 20170047453Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.Type: ApplicationFiled: April 7, 2016Publication date: February 16, 2017Inventors: Rongming Chu, Yu Cao, Zijian "Ray" Li, Adam J. Williams
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Patent number: 9559012Abstract: A semiconductor device includes a substrate, a III-nitride buffer layer on the substrate, an N-channel transistor including a III-nitride N-channel layer on one portion of the buffer layer, and a III-nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N-barrier layer has a wider bandgap than the N-channel layer, a P-channel transistor including a III-nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes, a III-nitride P-channel layer on top of the P-barrier layer, wherein the P-barrier layer has a wider bandgap than the P-channel layer, and a III-nitride cap layer doped with P-type dopants on top of the P-channel layer.Type: GrantFiled: August 31, 2015Date of Patent: January 31, 2017Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Yu Cao
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Publication number: 20170025267Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.Type: ApplicationFiled: October 7, 2016Publication date: January 26, 2017Inventors: Rongming Chu, Umesh Mishra, Rakesh K. Lal
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Patent number: 9496137Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.Type: GrantFiled: January 31, 2013Date of Patent: November 15, 2016Assignee: Transphorm Inc.Inventors: Rongming Chu, Umesh Mishra, Rakesh K. Lal
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Publication number: 20160308040Abstract: A transistor includes a stack of III-nitride semiconductor layers, the stack having a frontside and a backside, a source electrode in contact with the frontside of the stack, a drain electrode in contact with the backside of the stack, a trench extending through a portion of the stack, the trench having a sidewall, and a gate structure formed in the trench, including an AlN layer formed on the sidewall of the trench, an insulating cap layer formed on the AlN layer, and a gate electrode formed on the insulator cap layer and covering the sidewall of the trench.Type: ApplicationFiled: April 14, 2016Publication date: October 20, 2016Applicant: HRL Laboratories, LLCInventor: Rongming CHU
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Publication number: 20160293747Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: ApplicationFiled: June 14, 2016Publication date: October 6, 2016Inventors: Rongming Chu, Robert Coffie
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Publication number: 20160276161Abstract: A method of forming an Ohmic contact including forming a Ta layer in a contact area of a barrier, forming a Ti layer on the first Ta layer, and forming an Al layer on the Ti layer, wherein the barrier layer comprises AlGaN having a 10% to 40% Al composition and a thickness in a range between 30 ? to 100 ?, and wherein the barrier layer is on a channel layer comprising GaN.Type: ApplicationFiled: June 11, 2014Publication date: September 22, 2016Applicant: HRL LABORATORIES, LLCInventors: Mary Y. CHEN, Rongming Chu
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Patent number: 9419122Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.Type: GrantFiled: September 29, 2015Date of Patent: August 16, 2016Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Adam J. Williams, Dean C. Regan, Joel C. Wong
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Patent number: 9373699Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: GrantFiled: March 17, 2015Date of Patent: June 21, 2016Assignee: Transphorm Inc.Inventors: Rongming Chu, Robert Coffie
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Patent number: 9337332Abstract: A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.Type: GrantFiled: May 29, 2014Date of Patent: May 10, 2016Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Mary Y. Chen, Xu Chen, Zijian “Ray” Li, Karim S. Boutros
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Publication number: 20160064555Abstract: A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the substrate, a N-doped drift region being formed in said epitaxial layer; a P-doped base layer of said III-N material, formed on top of at least a portion of the drift region; a N-doped source region of said III-N material; formed on at least a portion of the base layer; and a gate trench having at least one vertical wall extending along at least a portion of the source region and at least a portion of the base layer; wherein at least a portion of the P-doped base layer along the gate trench is a layer of said P-doped III-N material that additionally comprises a percentage of aluminum.Type: ApplicationFiled: August 28, 2014Publication date: March 3, 2016Applicant: HRL LABORATORIES LLCInventor: Rongming CHU
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Publication number: 20150349117Abstract: A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.Type: ApplicationFiled: May 29, 2014Publication date: December 3, 2015Inventors: Rongming CHU, Mary Y. Chen, Xu Chen, Zijian "Ray" Li, Karim S. Boutros
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Patent number: 9202880Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.Type: GrantFiled: August 30, 2013Date of Patent: December 1, 2015Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Adam J. Williams, Dean C. Regan, Joel C. Wong
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Publication number: 20150318373Abstract: A diode and a method of making same has a cathode an anode and one or more semiconductor layers disposed between the cathode and the anode. A dielectric layer is disposed between at least one of the one or more semiconductor layers and at least one of the cathode or anode, the dielectric layer having one or more openings or trenches formed therein through which the at least one of said cathode or anode projects into the at least one of the one or more semiconductor layers, wherein a ratio of a total surface area of the one or more openings or trenches formed in the dielectric layer at the at least one of the one or more semiconductor layers to a total surface area of the dielectric layer at the at least one of the one or more semiconductor layers is no greater than 0.25.Type: ApplicationFiled: July 10, 2015Publication date: November 5, 2015Applicant: HRL Laboratories, LLCInventor: Rongming Chu
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Publication number: 20150311330Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: HRL Laboratories, LLCInventors: Zijian "Ray" LI, Rongming CHU