Abstract: A method and apparatus for locating a critical speed path in an integrated circuit. The operating frequency of the integrated circuit is increased until a logic error occurs in the integrated circuit. The propagation time of one clock signal within a circuit subblock of the integrated circuit is then increased until the logic error is eliminated. The propagation time of the clock signal is increased by enabling a delay circuit comprising a capacitor coupled to the clock signal. Another embodiment of the clock signal comprises a circuit that introduces contention on the clock signal line.

Abstract: A method for locating a critical speed path within a integrated digital circuit. First, the area containing the critical speed path is isolated by selectively enabling a delay of clock driver circuits in the integrated circuit. Isolating the location of the speed path consists of determining a source clock driver that clocks the source of the speed path and a destination clock driver that clocks the destination of the speed path. The possible data path that may be the speed path are then further narrowed down by examining a connection database that lists all the data paths between various circuit areas. Specifically, all the data paths that do not originate at a flip-flop clocked by the source clock driver and end at a flip-flop clocked by the destination clock driver are eliminated. Next, information from a logic simulation trace is examined. The exact time at which the error occurs is identified on the logic simulation trace.

Abstract: Integrated circuits must fulfill published timing specifications that have been given to customers. To fulfill published timing specifications, such as minimum valid time and maximum valid time, a circuit for adjusting the output signals from an integrated circuit is introduced. The circuit comprises in part a speed detector circuit that determines the speed of a clock signal. The speed detector circuit outputs a speed signal that defines how fast the integrated circuit is operating. The speed signal is passed to a speed adjustment circuit. The speed adjustment circuit delays, as appropriate, output signals from the integrated circuit. The output signals are delayed such that output signals fulfill the timing, specifications published in the data book for this integrated circuit. The speed adjustment circuit delays output signals by adding buffers along the data path which add propagation delay to the output data path.

Abstract: An improved local clock driver for locating race conditions within a integrated digital circuit. Highly integrated digital circuits have many local circuits and each local circuit has a local clock driver. The local clock driver strengthens and distributes a clock signal within the local circuit. The improved local clock driver introduces a controllable delay circuit in all the local clock drivers of the digital integrated circuit. By selectively delaying each local clock driver, clock skew problems that cause race conditions can be located. To compensate for such race conditions caused by clock skew problems, the delay circuit can be turned on in the receiving local block circuit.

Abstract: An apparatus for sampling logic states of a plurality of nodes of an integrated circuit. A selector circuit is coupled to the plurality of nodes of the integrated circuit and to a scan cell. The selector circuit comprises a plurality of control inputs, wherein each combination of logic states of the plurality of control inputs causes the selector circuit to output to the scan cell a logic value of a particular one of the nodes of the integrated circuit.

Abstract: An improved local clock driver for locating critical speed paths within a integrated digital circuit. Highly integrated digital circuits have many local circuits and each local circuit has a local clock driver. The local clock driver strengthens and distributes a clock signal within the local circuit. The improved local clock driver introduces a controllable delay circuit in all the local clock drivers of the digital integrated circuit. By selectively delaying each local clock driver, critical speed paths can be located. To compensate for critical speed paths, the delay circuit can be turned on in the receiving local block circuit.

Abstract: A data signal is input into an integrated circuit and the data signal is transmitted through a series of logic gates that cause a propagation delay. An external clock line associated with the data signal is also inputted into the integrated circuit. The external clock signal is passed through a delay shifter that adds a controllable amount of delay to the clock signal. The amount of delay added to the clock signal should equal the total amount of propagation delay added to the data signal. The clock signal is then also transmitted through a phase-lock loop to stabilize the clock signal. The delayed internal clock signal is then used to clock the data signal which has been transmitted through a series of logic gates that have added propagation delay. Since the internal clock signal has been delayed an equal amount as the data signal, the data signal will be clocked at an appropriate time.

Abstract: An integrated circuit for deskewing and adjusting a delay of a synthesized waveform. The synthesized waveform is initially produced by a digital-to-time domain converter which is coupled to a synchronous delay line and a pattern ROM through a shifter and a pattern register. The synchronous delay line generates a plurality of taps in response to a reference signal. Each one of the taps has a unit delay and is coupled to the digital-to-time domain converter. The integrated circuit which deskews and adjusts the delay of the synthesized waveform comprises a microdelay calibration circuit, a deskew control circuit, and a delay interpolation circuit. The microdelay calibration circuit is coupled to the taps of the synchronous delay line and the deskew control circuit. The deskew control circuit is coupled the shifter to perform coarse deskew operations. The deskew control circuit is further coupled to the delay interpolation circuit to perform fine deskew operations.