Abstract: A system and method for performing computational processing by a systolic array. The systolic array including an array of processing elements (PEs) arranged in rows and columns; logic to perform a horizontal shift operation, wherein the horizontal shift operation is performed across the entire systolic array; and logic to mark columns of PEs as enabled or disabled, wherein the systolic array is horizontally divided into horizontal groups, and wherein when performing the horizontal shift operation, valid data that crosses from a first column of PEs of a first horizontal group to a second column of PEs of a second horizontal group is invalidated, wherein the first horizontal group is adjacent to the second horizontal group.

Abstract: A system and method for performing computational processing by a systolic array. The systolic array including an array of processing elements (PEs) arranged in rows and columns; logic to perform a horizontal shift operation, wherein the horizontal shift operation is performed across the entire systolic array; and logic to mark columns of PEs as enabled or disabled, wherein the systolic array is horizontally divided into horizontal groups, and wherein when performing the horizontal shift operation, valid data that crosses from a first column of PEs of a first horizontal group to a second column of PEs of a second horizontal group is invalidated, wherein the first horizontal group is adjacent to the second horizontal group.

Abstract: A logic circuit in a processor including a plurality of input registers, each for storing a vector containing data elements, a coefficient register for storing a vector containing N coefficients, an output register for storing a result vector, and an arithmetic unit configured to: obtain a pattern for selecting N data elements from the plurality of input registers, select a plurality of groups of N data elements from the plurality of input registers in parallel, wherein each group is selected in accordance with the pattern, and wherein each group is shifted with respect to a previous selected group, perform an arithmetic operation between each of the selected groups and the coefficients in parallel, and store results of the arithmetic operations in the output register.

Abstract: A system and method for preventing cache contention for a cache including a plurality of ways and a separate port for each way, the method including: obtaining, in a core of a processor, a multidimensional coefficient array of a multidimensional filter, and pointers to data elements from a plurality of rows of a multidimensional data array, and loading the plurality of rows into the cache, where each row is stored in a different way of the cache.

Abstract: A logic circuit in a processor including a plurality of input registers, each for storing a vector containing data elements, a coefficient register for storing a vector containing N coefficients, an output register for storing a result vector, and an arithmetic unit configured to: obtain a pattern for selecting N data elements from the plurality of input registers, select a plurality of groups of N data elements from the plurality of input registers in parallel, wherein each group is selected in accordance with the pattern, and wherein each group is shifted with respect to a previous selected group, perform an arithmetic operation between each of the selected groups and the coefficients in parallel, and store results of the arithmetic operations in the output register.

Abstract: A system and method of data transfer that collapses a multi-dimensional data array while preserving neighboring connectivity. One or more program instructions may be received that request input data comprising a sub-set of data elements from a first data array in an external memory. The sub-set of data elements may be transferred from the first data array in the external memory to a second data array in an internal memory. The retrieved sub-set of requested data elements may be stored in the second array in respective positions translated from the positions in the first array by a plurality of omitted rows and columns from the first data array from which no data elements are requested.

Abstract: A system and method of data transfer that collapses a multi-dimensional data array while preserving neighboring connectivity. One or more program instructions may be received that request input data comprising a sub-set of data elements from a first data array in an external memory. The sub-set of data elements may be transferred from the first data array in the external memory to a second data array in an internal memory. The retrieved sub-set of requested data elements may be stored in the second array in respective positions translated from the positions in the first array by a plurality of omitted rows and columns from the first data array from which no data elements are requested.

Abstract: A system and method for controlling video compression quantization comprising generating a quantizer scale offset based on diagonal frequencies of luminance components of a data block samples, luminance intensity of the samples and motion activity of the data block, adjusting a first quantizer scale using the quantizer scale offset to receive a second quantizer scale and quantizing the data block using the second quantizer scale.

Abstract: Embodiments of the invention are directed to a system and method for dynamically defining a search area in a previously-coded reference picture during motion estimation in video encoding. The method includes receiving a sequence of pictures that are divided into a plurality of digital data blocks and defining for a currently-coded data block of a currently coded-picture, a search area within a previously-coded reference picture based on one or more search areas associated with previously-coded data blocks of the currently-coded picture, for example the left data block and the upper data block and further on a search area associated with a previously-coded data block of the reference picture that is co-positioned with the currently coded data block.

Abstract: A system, processor, data structure, and method are provided for processing multiple dimension data. A plurality of data elements stored in different dimensions in a sub-array of a first multiple dimension data array may be identified or determined to be correlated. The plurality of correlated data elements in different dimensions may be mapped to sequential positions in a single dimension of a second data array. In each computational cycle a plurality of data elements that are sequentially stored in the single dimension may be iteratively retrieved from the data array until at least all the correlated data elements are retrieved. The correlated data elements may be processed.

Abstract: A system and method for controlling video compression quantization comprising generating a quantizer scale offset based on diagonal frequencies of luminance components of a data block samples, luminance intensity of the samples and motion activity of the data block, adjusting a first quantizer scale using the quantizer scale offset to receive a second quantizer scale and quantizing the data block using the second quantizer scale.

Abstract: An image compression method is provided including separating an image into a plurality of color channel sub-images processing each of the color channel sub-images by sub-sampling the sub-image transform coding the sub-sampled sub-image decoding the transform-coded image forming a plurality of square groupings of pixels in the decoded image predicting a value for a pixel within each of the x-shaped groupings determining a prediction error for each predicted pixel value within each of the square groupings coding the prediction error forming a plurality of at least partly diamond-shaped groupings of pixels in the decoded image predicting a value for a pixel within each of the diamond-shaped groupings and combining each of the processed color channel sub-images with the coded prediction errors, thereby forming a compressed image.

Abstract: The present invention is embodied in a data compression encoder for use with the discrete cosine transform compression process. The invention enhances compression using the discrete cosine transform by utilizing a prediction engine that breaks the data received into predicted and unpredicted portions. The predicted portions are excluded from the discrete cosine transform reducing the time-required to compress a file. The prediction engine relies, in part, upon look-up tables that are used to determine the predicted blocks. A table build engine and database compiler are used to create the look-up tables.

Abstract: The present invention is embodied in a system for building a data compression encoder for use with the discrete cosine transform compression process. The invention results in enhanced compression using the discrete cosine transform by constructing a prediction engine that breaks the data received into predicted and unpredicted portions. The predicted portions are excluded from the discrete cosine transform reducing the time required to compress a file. The prediction engine relies, in part, upon look-up tables that are developed by the present invention to determine the predicted blocks. A table build engine and database compiler are used to create the look-up tables.