Patents by Inventor Roni Rosner

Roni Rosner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11847497
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: Michael Behar, Moshe Maor, Ronen Gabbai, Roni Rosner, Zigi Walter, Oren Agam
  • Publication number: 20230333913
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 19, 2023
    Inventors: Michael Behar, Moshe Maor, Ronen Gabbai, Roni Rosner, Zigi Walter, Oren Agam
  • Patent number: 11675630
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: June 13, 2023
    Assignee: INTEL CORPORATION
    Inventors: Michael Behar, Moshe Maor, Ronen Gabbai, Roni Rosner, Zigi Walter, Oren Agam
  • Publication number: 20230178114
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating variants/versions of an audio digital component and providing a particular variant for displaying/playing on a client device. Methods can include receiving a request to generate a template for an audio digital component. Based on information in the request, the template can be generated. A first set of media data items can be linked to static media data blocks in the template. Based on the template, variants of the audio digital component can be generated and for each, media data items can be linked to the dynamic media data blocks. A request for the audio digital component can be received from a client device. A set of signals can be obtained from the client device, based on which, a particular variant of the audio digital component can be provided for display on the device.
    Type: Application
    Filed: September 10, 2020
    Publication date: June 8, 2023
    Inventors: Nathaniel Marc Biggs, Roni Rosner, Natalie Marion Bennett, Emily Ryan, Ruoxi Mao, Yeo Jin Ree
  • Patent number: 11422939
    Abstract: Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Israel Diamand, Ravi K. Venkatesan, Shlomi Shua, Oz Shitrit, Michael Behar, Roni Rosner
  • Publication number: 20220197703
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 23, 2022
    Inventors: Michael Behar, Moshe Maor, Ronen Gabbai, Roni Rosner, Zigi Walter, Oren Agam
  • Publication number: 20220066923
    Abstract: Systems, apparatuses and methods may provide for technology that determines runtime memory requirements of an artificial intelligence (AI) application, defines a remote address range for a plurality of memories based on the runtime memory requirements, wherein each memory in the plurality of memories corresponds to a processor in a plurality of processors, and defines a shared address range for the plurality of memories based on the runtime memory requirements, wherein the shared address range is aliased. In one example, the technology configures memory mapping hardware to access the remote address range in a linear sequence and access the shared address range in a hashed sequence.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Inventors: Zigi Walter, Roni Rosner, Michael Behar
  • Patent number: 11231963
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 25, 2022
    Assignee: INTEL CORPORATION
    Inventors: Michael Behar, Moshe Maor, Ronen Gabbai, Roni Rosner, Zigi Walter, Oren Agam
  • Patent number: 11151074
    Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Israel Diamand, Roni Rosner, Ravi Venkatesan, Shlomi Shua, Oz Shitrit, Henrietta Bezbroz, Alexander Gendler, Ohad Falik, Zigi Walter, Michael Behar, Shlomi Alkalay
  • Publication number: 20210200675
    Abstract: Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Applicant: Intel Corporation
    Inventors: Israel DIAMAND, Ravi K. VENKATESAN, Shlomi SHUA, Oz SHITRIT, Michael BEHAR, Roni ROSNER
  • Publication number: 20190370084
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Michael Behar, Moshe Maor, Ronen Gabbai, Roni Rosner, Zigi Walter, Oren Agam
  • Publication number: 20190370074
    Abstract: An apparatus includes a communication processor to receive configuration information from a producing compute building block; a credit generator to generate a number of credits for the producing compute building block corresponding to the configuration information, the configuration information including characteristics of a buffer; a source identifier to analyze a returned credit to determine whether the returned credit originates from the producing compute building block or a consuming compute building block; and a duplicator to, when the returned credit originates from the producing compute building block, multiply the returned credit by a first factor, the first factor indicative of a number of consuming compute building blocks identified in the configuration information.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Roni Rosner, Moshe Maor, Michael Behar, Ronen Gabbai, Zigi Walter, Oren Agam
  • Publication number: 20190370209
    Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Israel Diamand, Roni Rosner, Ravi Venkatesan, Shlomi Shua, Oz Shitrit, Henrietta Bezbroz, Alexander Gendler, Ohad Falik, Zigi Walter, Michael Behar, Shlomi Alkalay
  • Publication number: 20190370076
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable dynamic processing of a predefined workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to obtain a workload node, the workload node associated with a first amount of data, the workload node to be executed at a first one of the one or more computational building blocks; an analyzer to: determine whether the workload node is a candidate for early termination; and in response to determining that the workload node is a candidate for early termination, set a flag associated with a tile of the first amount of data; and a dispatcher to, in response to the tile being transmitted from the first one of the one or more computational building blocks to a buffer, stop execution of the workload node.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Michael Behar, Oren Agam, Ronen Gabbai, Zigi Walter, Roni Rosner, Moshe Maor
  • Publication number: 20190370073
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Michael Behar, Moshe Maor, Ronen Gabbai, Roni Rosner, Zigi Walter, Oren Agam
  • Patent number: 7802076
    Abstract: An optimization unit to search for two or more candidate instructions in an instruction trace and to merge the two or more candidate instructions into a single instruction with multiple data (SIMD) according to a depth of a trace dependency and a common operation code of the two or more candidate instructions.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: September 21, 2010
    Assignee: Intel Corporation
    Inventors: Yoav Almog, Roni Rosner, Ronny Ronen
  • Patent number: D941310
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: January 18, 2022
    Assignee: GOOGLE LLC
    Inventors: Ruoxi Mao, Natalie Bennett, Emily Ryan, Nathaniel Biggs, Roni Rosner, Yeo Jin Ree, Adam Becker
  • Patent number: D941311
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: January 18, 2022
    Assignee: GOOGLE LLC
    Inventors: Ruoxi Mao, Natalie Bennett, Emily Ryan, Nathaniel Biggs, Roni Rosner, Yeo Jin Ree, Adam Becker
  • Patent number: D941312
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: January 18, 2022
    Assignee: GOOGLE LLC
    Inventors: Ruoxi Mao, Natalie Bennett, Emily Ryan, Nathaniel Biggs, Roni Rosner, Yeo Jin Ree, Adam Becker
  • Patent number: D949882
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 26, 2022
    Assignee: GOOGLE LLC
    Inventors: Ruoxi Mao, Natalie Bennett, Emily Ryan, Nathaniel Biggs, Roni Rosner, Yeo Jin Ree, Adam Becker