Abstract: A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.

Abstract: Methods, systems, and apparatuses include moving a portion of memory to a garbage pool in response to determining that the portion of memory is invalid. The portion of memory is erased in response to determining that the portion of memory is invalid. A request to move an additional portion of memory to a free pool from the garbage pool is received. A free pool includes a queue including erased portions of memory, which serve as next portions of memory to fulfill subsequent cursor requests. The erased portion of memory is moved from the garbage pool to the free pool.

Abstract: A system with a memory device and a processing device operatively coupled with the memory device, to perform operations including identifying a lifecycle state associated with a segment of the memory device, selecting, based on the lifecycle state, an erase policy for performing an erase operation with respect to the segment, and causing the erase operation to be performed with respect to the segment in accordance with the erase policy.

Abstract: A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.

Abstract: Control logic in a memory device receives a request to perform a memory access operation on a memory array of the memory device and determines an operating temperature of the memory device. The control logic further modifies a default magnitude of a source voltage signal based on the operating temperature to a form a modified source voltage signal, causes the modified source voltage signal to be applied to the memory array, and performs the memory access operation on the memory array.

Abstract: A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.

Abstract: A system includes a memory device including a memory array including a plurality of wordline groups and control logic, operatively coupled with the memory array, to perform operation including causing a first erase verify to be performed sequentially with respect to each wordline group of the plurality of wordline groups, identifying a set of failing wordline groups determined to have failed the first erase verify, and causing a second erase verify to be performed sequentially with respect to each wordline group of the set of failing wordline groups.

Abstract: A system includes a memory device including a memory array including a plurality of wordline groups and control logic, operatively coupled with the memory array, to perform operation including causing a first erase verify to be performed sequentially with respect to each wordline group of the plurality of wordline groups, identifying a set of failing wordline groups determined to have failed the first erase verify, and causing a second erase verify to be performed sequentially with respect to each wordline group of the set of failing wordline groups.