Patents by Inventor Ronnen Andrew Roy
Ronnen Andrew Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7102234Abstract: A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.Type: GrantFiled: April 19, 2004Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Ronnen Andrew Roy, Yun Yu Wang
-
Patent number: 7081676Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: GrantFiled: October 22, 2003Date of Patent: July 25, 2006Assignee: International Business Machines CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
-
Patent number: 6987050Abstract: A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.Type: GrantFiled: July 11, 2001Date of Patent: January 17, 2006Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Kevin Kok Chan, Guy Moshe Cohen, Christian Lavoie, Ronnen Andrew Roy, Paul Michael Solomon
-
Patent number: 6809030Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: GrantFiled: June 28, 2002Date of Patent: October 26, 2004Assignee: International Business Machines CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
-
Publication number: 20040195695Abstract: A method of reducing the contact resistance of metal suicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.Type: ApplicationFiled: April 19, 2004Publication date: October 7, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral,, Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Ronnen Andrew Roy, Yun Yu Wang
-
Patent number: 6753606Abstract: A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.Type: GrantFiled: November 27, 2001Date of Patent: June 22, 2004Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Ronnen Andrew Roy, Yun Yu Wang
-
Publication number: 20040087160Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: ApplicationFiled: October 22, 2003Publication date: May 6, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul David Agnello, Cyril Cabral, Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
-
Patent number: 6727135Abstract: A complementary metal oxide semiconductor (CMOS) device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a method of manufacturing the same are disclosed. Specifically, the CMOS device includes a plurality of patterned gate stack regions formed on a surface of a semiconductor substrate. Each plurality of patterned gate stack regions includes an L-shaped nitride spacer formed on exposed vertical sidewalls thereof, the L-shaped nitride spacer having a vertical element and a horizontal element, wherein the horizontal element is formed on a portion of the substrate that abuts each patterned gate stack region. Silicide contacts are located on other portions of the semiconductor substrate between adjacent patterned gate stack regions not containing the horizontal element of the L-shaped nitride spacer.Type: GrantFiled: June 18, 2003Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Kam Leung Lee, Ronnen Andrew Roy
-
Patent number: 6716708Abstract: A method (and resultant structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of said silicon-containing region, includes implanting Ge into the silicon-containing region, forming a blanket metal-silicon mixture layer over the silicon-containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.Type: GrantFiled: November 20, 2002Date of Patent: April 6, 2004Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Kevin Kok Chan, Guy Moshe Cohen, Kathryn Wilder Guarini, Christian Lavoie, Ronnen Andrew Roy, Paul Michael Solomon
-
Publication number: 20030209765Abstract: A complementary metal oxide semiconductor (CMOS) device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a method of manufacturing the same are disclosed. Specifically, the CMOS device includes a plurality of patterned gate stack regions formed on a surface of a semiconductor substrate. Each plurality of patterned gate stack regions includes an L-shaped nitride spacer formed on exposed vertical sidewalls thereof, the L-shaped nitride spacer having a vertical element and a horizontal element, wherein the horizontal element is formed on a portion of the substrate that abuts each patterned gate stack region. Silicide contacts are located on other portions of the semiconductor substrate between adjacent patterned gate stack regions not containing the horizontal element of the L-shaped nitride spacer.Type: ApplicationFiled: June 18, 2003Publication date: November 13, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kam Leung Lee, Ronnen Andrew Roy
-
Patent number: 6614079Abstract: A complementary metal oxide semiconductor (CMOS) device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a method of manufacturing the same are disclosed. Specifically, the CMOS device includes a plurality of patterned gate stack regions formed on a surface of a semiconductor substrate. Each plurality of patterned gate stack regions includes an L-shaped nitride spacer formed on exposed vertical sidewalls thereof, the L-shaped nitride spacer having a vertical element and a horizontal element, wherein the horizontal element is formed on a portion of the substrate that abuts each patterned gate stack region. Silicide contacts are located on other portions of the semiconductor substrate between adjacent patterned gate stack regions not containing the horizontal element of the L-shaped nitride spacer.Type: GrantFiled: July 19, 2001Date of Patent: September 2, 2003Assignee: International Business Machines CorporationInventors: Kam Leung Lee, Ronnen Andrew Roy
-
Publication number: 20030132487Abstract: A method (and resultant structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of said silicon-containing region, includes implanting Ge into the silicon-containing region, forming a blanket metal-silicon mixture layer over the silicon-containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.Type: ApplicationFiled: November 20, 2002Publication date: July 17, 2003Applicant: International Business Machines CorporationInventors: Cyril Cabral, Kevin Kok Chan, Guy Moshe Cohen, Kathryn Wilder Guarini, Christian Lavoie, Ronnen Andrew Roy, Paul Michael Solomon
-
Patent number: 6555880Abstract: A semiconductor structure includes raised source and drain regions, where the raised source and drain regions are facet free and unconstrained to have a shape conforming to a same crystallographic axes with respect to each other.Type: GrantFiled: June 7, 2001Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Kevin Kok Chan, Guy Moshe Cohen, Kathryn Wilder Guarini, Christian Lavoie, Ronnen Andrew Roy, Paul Michael Solomon
-
Publication number: 20030068883Abstract: A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.Type: ApplicationFiled: November 5, 2002Publication date: April 10, 2003Applicant: International Business Machines CorporationInventors: Atul Champaklal Ajmera, Cyril Cabral, Roy Arthur Carruthers, Kevin Kok Chan, Guy Moshe Cohen, Paul Michael Kozlowski, Christian Lavoie, Joseph Scott Newbury, Ronnen Andrew Roy
-
Publication number: 20030015762Abstract: A complementary metal oxide semiconductor (CMOS) device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a method of manufacturing the same are disclosed. Specifically, the CMOS device includes a plurality of patterned gate stack regions formed on a surface of a semiconductor substrate. Each plurality of patterned gate stack regions includes an L-shaped nitride spacer formed on exposed vertical sidewalls thereof, the L-shaped nitride spacer having a vertical element and a horizontal element, wherein the horizontal element is formed on a portion of the substrate that abuts each patterned gate stack region. Silicide contacts are located on other portions of the semiconductor substrate between adjacent patterned gate stack regions not containing the horizontal element of the L-shaped nitride spacer.Type: ApplicationFiled: July 19, 2001Publication date: January 23, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kam Leung Lee, Ronnen Andrew Roy
-
Patent number: 6503833Abstract: A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.Type: GrantFiled: November 15, 2000Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Atul Champaklal Ajmera, Cyril Cabral, Jr., Roy Arthur Carruthers, Kevin Kok Chan, Guy Moshe Cohen, Paul Michael Kozlowski, Christian Lavoie, Joseph Scott Newbury, Ronnen Andrew Roy
-
Publication number: 20020185691Abstract: A method (and resultant structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of said silicon-containing region, includes implanting Ge into the silicon-containing region, forming a blanket metal-silicon mixture layer over the silicon-containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.Type: ApplicationFiled: June 7, 2001Publication date: December 12, 2002Applicant: International Business Machines CorporationInventors: Cyril Cabral, Kevin Kok Chan, Guy Moshe Cohen, Kathryn Wilder Guarini, Christian Lavoie, Ronnen Andrew Roy, Paul Michael Solomon
-
Publication number: 20020182836Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2layer in said structure.Type: ApplicationFiled: June 28, 2002Publication date: December 5, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul David Agnello, Cyril Cabral, Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
-
Publication number: 20020151158Abstract: Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.Type: ApplicationFiled: June 11, 2002Publication date: October 17, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Roy Arthur Carruthers, James McKell Edwin Harper, Paul Michael Kozlowski, Christian Lavoie, Joseph Scott Newbury, Ronnen Andrew Roy
-
Patent number: 6440851Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: GrantFiled: October 12, 1999Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang