Abstract: A symmetric multiprocessor system includes a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface and a first outbound interface associated with the first processor, a first task queue accessible for reading by the first processor, a second inbound interface and a second outbound interface associated with the second processor, and a second task queue accessible for reading by at least the first processor. The first inbound interface receives incoming packets and has a first input buffer maintaining a first input queue of the packets for processing by the first processor. The first outbound interface receives packets from the first processor and transmits outgoing packets. The first task queue receives packets output from at least the second processor and maintains another input queue of the packets for processing by the first processor and which are outgoing from the first outbound interface.

Abstract: A high reliability computer system includes a first processing engine (PE), a first memory and a third memory both accessible by the first PE, a second PE, and a second memory and a fourth memory both accessible by the second PE. The first memory contains initialization information for the first PE. The third memory has a location for storing an enable password or a surrogate therefor for the first PE. The second memory contains initialization information for the second PE. The computer system also includes circuitry for switching control of the system from the first PE to the second PE upon detection of a failure of the first PE, and a password passer writing the enable password or a surrogate therefor of the first PE to the fourth memory. Alternatively, a network system includes an authentication, authorization and accounting (AAA) or any other password server having a database for maintaining an enable password for a high reliability computer system.

Abstract: A symmetric multiprocessor system includes a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface and a first outbound interface associated with the first processor, a first task queue accessible for reading by the first processor, a second inbound interface and a second outbound interface associated with the second processor, and a second task queue accessible for reading by at least the first processor. The first inbound interface receives incoming packets and has a first input buffer maintaining a first input queue of the packets for processing by the first processor. The first outbound interface receives packets from the first processor and transmits outgoing packets. The first task queue receives packets output from at least the second processor and maintains another input queue of the packets for processing by the first processor and which are outgoing from the first outbound interface.

Abstract: A high reliability computer system includes a first and a second processing engine (PE), circuitry for switching control of the system from the first PE operating as a primary PE to the second PE upon detection of a failure of the first PE, at least one shared resource associated with both the first and second PEs, at least one dedicated resource associated with the first PE and at least one dedicated resource associated with the second PE, a database associated with and accessible by one of the first and second PEs and a configuration engine. The database contains initialization information for the one PE, including a first class of instructions affecting the shared resource and a second class of instructions affecting the dedicated resource of the one PE. The second class of instructions includes setting an enable password or a surrogate therefor for the one PE. The configuration engine is associated with the one PE and is operable in one of a first mode and a second mode.

Abstract: Data storage units, such as flash memory, nonvolatile random access memory and like, are provided with information stored therein, or physically coupled thereto, which indicates, or can be used to determine, remaining or impending end of lifetime of the data storage unit or its components. In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.