Abstract: A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal is comprised of a logic circuit for receiving first and second signals produced by the locked loop. The logic circuit determines if a predetermined phase relationship exists between the first and second signals and produces an output signal indicative of that determination.

Abstract: A loss of signal detector for use with a delay-locked loop of the type which produces a plurality of output signals in response to a clock signal is comprised of a first monitor for receiving a first one of the plurality of output signals from the delay-locked loop. The second monitor receives a second one of the plurality of output signals from the delay-locked loop. The first and second signals are preferably, but not necessarily, in quadrature with respect to one another. Each of the monitors is clocked with a clock signal and the inverse of the clock signal. A plurality of logic gates is responsive to the first and second monitors for producing an output signal.

Abstract: A data and command latching circuit includes a delay-locked loop driven by a continuous reference clock signal that generates a delayed output clock signal having a delay controlled by the delay-locked loop. The latching circuit also includes a variable delay circuit external to the delay-locked loop that is driven by a discontinuous reference clock signal. Delay of the external delay circuit is controlled by a control voltage output from the delay-locked loop, so that the delays of the external delay circuit are determined with reference to the continuous reference clock signal. The delayed clock signals from the delay-locked loop activate control data latches to latch control data arriving at the latch circuit. The delayed signals from the variable voltage circuit activate data latches to latch data arriving at the latch circuit.

Abstract: An input voltage controlled oscillator circuit for a digital video time base corrector used to process television signals to remove time base errors introduced during signal recording, reproducing, or transmission. In the time base corrector, incoming video signals are converted from analog-to-digital form, temporarily stored in a memory unit at a clocking rate which varies in a manner generally proportional to the time base errors, and the stored signals are fetched at a standard clocking rate.The input voltage controlled oscillator circuit generates the clock signals for performing the analog-to-digital conversion and for storing the digital signals in the memory unit. The frequency of the clock signals varies in accordance with the time base errors in the composite sync and burst portions of the incoming video signals.

Abstract: A sequence control unit for a digital video time base corrector used to process television signals to remove time base errors introduced during signal recording, reproducing, or transmission. In the time base corrector, incoming video signals are converted from analog to digital form, temporarily stored in a memory unit at a clocking rate which varies in a manner generally proportional to the time base errors, and the stored signals are fetched at a standard clocking rate. The sequence control unit controls contemporaneous storing and fetching from different portions of the memory unit and includes circuitry for preventing application of both store and fetch signals to the same memory unit portion when the accumulated time base error would cause such an overlap condition.