Abstract: A cryptocurrency miner includes a control power supply, a compute power supply, a compute module, and a controller. The compute module includes control circuitry powered based on first power supplied by the control power supply and a compute engine powered based on second power supplied by the compute power supply. The controller causes the control power supply to apply the first power to the control circuitry. The controller further causes the compute power supply to apply the second power to the compute engine after initialization of the control circuitry.

Abstract: Distribution of jobs among compute modules of a cryptocurrency miner is disclosed. A cryptocurrency miner may include a serial bus, compute modules, and a controller. The controller may receive a candidate block, generate jobs based on the candidate block, and distribute the jobs among the plurality of compute modules by issuing a job submit command to the compute modules via the serial bus. The job submit command may comprise block sets that at least partially define the plurality of jobs. The block sets may include a plurality of midstates that correspond to a plurality of message blocks.

Abstract: Multicast reading of compute module registers is disclosed. A cryptocurrency miner comprises a serial bus, compute modules, and a miner controller coupled to the compute modules via the serial bus. The miner controller issues a multicast read command via the serial bus and receives values from respective registers of a first plurality of compute modules. The miner controller may initialize the compute modules with register set configurations that identify respective registers and latencies for returning values from such registers.

Abstract: A cryptocurrency miner includes compute modules and a controller. Each compute module includes a stats store, a manager, and compute engines. The controller is coupled to the compute modules via a serial bus and distributes one or more jobs to the compute modules via the serial bus. Each manager distributes jobs received by its respective compute module among the compute engines of its respective compute module. Each compute engine processes a job and reports a candidate hit found by processing the job. Each manager validates a candidate hit reported by one of the compute engines of its respective compute module, reports the validated candidate hit to the controller; and updates statistical information in the stats store of its respective compute module based on validation of the candidate hit.

Abstract: A cryptocurrency miner includes a serial bus, compute modules, and a controller. Each compute module includes upstream ports, downstream ports, a pass-through buffer coupling the upstream ports to the downstream ports, and a serial bus interface coupled to the serial bus via the first upstream ports and the first downstream ports. The controller controls operation of the compute modules via commands on the serial bus. The serial bus includes bus segments between respective upstream and downstream ports of the compute modules.

Abstract: A cryptocurrency miner includes a power supply, a network interface, a compute module, and a controller. The compute module includes compute engine stories coupled in series with the power supply. Each compute engine story includes compute engines coupled in parallel between a voltage input node and voltage output node of the respective compute engine story. The controller receives, via the network interface, a job from a pool server of a mining pool and distributes aspects of the job to the compute engine stories.

Abstract: A cryptocurrency miner includes a control power supply, a compute power supply, a compute module, and a controller. The compute module includes control circuitry powered based on first power supplied by the control power supply and a compute engine powered based on second power supplied by the compute power supply. The controller causes the control power supply to apply the first power to the control circuitry. The controller further causes the compute power supply to apply the second power to the compute engine after initialization of the control circuitry.

Abstract: A network interface adapter includes a memory interface, for coupling to a memory containing a first data packet composed in accordance with a first communication protocol, and a network interface, for coupling to a packet communication network. Packet processing circuitry in the adapter reads the first data packet from the memory via the memory interface, computes a checksum of the first data packet, inserts the checksum in the first data packet in accordance with the first communication protocol, and encapsulates the first data packet in a payload of a second data packet in accordance with a second communication protocol applicable to the packet communication network, so as to transmit the second data packet over the network via the network interface. The circuitry likewise computes checksums of incoming encapsulated data packets from the network.