Abstract: An apparatus is described that facilitates network security and network traffic monitoring through processing of network traffic in accordance with provisioned rules and policies. The apparatus includes a set of microcode controlled state machines, each of which applies one or more rules to input network traffic. A distribution circuit routes individual network traffic segments derived from input network traffic to the set of microcode controlled state machines, so that each individual segment is processed in accordance with microcode stored in an associated control store. Each microcode controlled state machine includes a computation kernel operating in accordance with the microcode. An aggregation circuit routes the resulting processed individual network traffic segments in accordance with an output routing policy to produce output network traffic corresponding to the original input network traffic.

Abstract: An apparatus is described that facilitates network security and network traffic monitoring through processing of network traffic in accordance with provisioned rules and policies. The apparatus includes a set of microcode controlled state machines, each of which includes a computation kernel operating in accordance with microcode stored in a control store. A distribution circuit routes individual network traffic segments derived from input network traffic to the set of microcode controlled state machines, so that at least one of the microcode controlled state machines applies a rule encoded in the microcode to the individual network traffic segments to produce modification instructions. A circuit performs a modification of the input network traffic based on the modification instructions from the at least one microcode controlled state machine to produce output network traffic.

Abstract: An apparatus is described that facilitates selective mirroring through processing of network traffic in accordance with provisioned rules and policies. The apparatus includes a port included in a set of at least one port, wherein each port in the set receives input traffic, a data processor that processes input data from the set of at least one port to generate mirrored data, based on rules with bitwise granularity across a header and a payload of the input data, and a mirror port selectable from the set of at least one port that transmits output traffic corresponding to the mirrored data. Advantageously, the apparatus provides an architectural framework well suited to a low cost, high speed, robust implementation of selective mirroring that enables flexible, advanced network security and monitoring features and network traffic analysis.

Abstract: An apparatus is described that provides security and monitoring in a networking architecture. One embodiment of the apparatus includes a physical layer interface that includes a physical layer receiver and a decoder for converting physical layer data from the physical layer receiver to data link layer information, wherein the decoder processes input data corresponding to the physical layer data based on rules conditioned on higher layer information to generate output data corresponding to the data link layer information; and a controller for provisioning the physical layer interface. Advantageously, the apparatus provides an architectural framework well suited to a low cost, high speed, robust implementation of flexible, advanced network security and monitoring features, traffic management, and network traffic analysis.

Abstract: A method and apparatus may be provided for providing performance verification/analysis of a full-chip design. This may include performing an analysis on a first block of the full-chip design. Data (such as a waveform output from a pin of the block) may be captured while performing the analysis. This captured data may be utilized when performing an analysis of the full-chip design. Features of an interconnect between the first block and a second block may be determined using the captured data.

Abstract: A method and apparatus may be provided for providing performance verification/analysis of a full-chip design. This may include performing an analysis on a first block of the full-chip design. Data (such as a waveform output from a pin of the block) may be captured while performing the analysis. This captured data may be utilized when performing an analysis of the full-chip design. Features of an interconnect between the first block and a second block may be determined using the captured data.

Abstract: A design rule checker for verifying that an integrated circuit design meets one or more geometrical constraints, the integrated circuit design being expressed as a graph data structure having at least a root node connected by a plurality of paths to one or more leaf nodes so that a single leaf node can represent multiple instances of a geometrical shape.