Patents by Inventor Rose Fasano Kopf
Rose Fasano Kopf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11394097Abstract: Composite substrate for a waveguide for RF signals having a signal frequency, wherein said composite substrate comprises at least a first layer of dielectric material and a second layer of dielectric material, and at least one conductor layer of an electrically conductive material arranged between said first layer and said second layer, wherein a layer thickness of said at least one conductor layer is smaller than about 120 percent of a skin depth of said RF signals within said electrically conductive material of said conductor layer.Type: GrantFiled: April 27, 2018Date of Patent: July 19, 2022Assignee: NOKIA SOLUTIONS AND NETWORKS OYInventors: Senad Bulja, Rose Fasano Kopf, Pawel Rulikowski, Majid Norooziarab
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Publication number: 20200153076Abstract: Composite substrate (1300; CS) for radio frequency, RF, signals comprising at least a first layer (1310; 1310a) of di-electric material and a second layer (1320; 1320a) of dielectric material, and at least one conductor layer (1330; 1330a) of an electrically conductive material arranged between said first layer (1310; 1310a) and said second layer (1320; 1320a), wherein said first layer (1310; 310a) and said second layer (1320; 1320a) and said conductor layer (1330; 1330a) each comprise optically transparent material.Type: ApplicationFiled: May 15, 2018Publication date: May 14, 2020Inventors: Senad Bulja, Wolfgang Templ, Rose Fasano Kopf, Florian Pivit
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Publication number: 20200127357Abstract: Composite substrate for a waveguide for RF signals having a signal frequency, wherein said composite substrate comprises at least a first layer of dielectric material and a second layer of dielectric material, and at least one conductor layer of an electrically conductive material arranged between said first layer and said second layer, wherein a layer thickness of said at least one conductor layer is smaller than about 120 percent of a skin depth of said RF signals within said electrically conductive material of said conductor layer.Type: ApplicationFiled: April 27, 2018Publication date: April 23, 2020Inventors: Senad Bulja, Rose Fasano Kopf, Pawel Rulikowski, Majid Norooziarab
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Patent number: 7595249Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.Type: GrantFiled: September 29, 2008Date of Patent: September 29, 2009Assignee: Alcatel-Lucent USA Inc.Inventors: Young-Kai Chen, Lay-Lay Chua, Vincent Etienne Houtsma, Rose Fasano Kopf, Andreas Leven, Chun-Ting Liu, Wei-Jer Sung, Yang Yang
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Patent number: 7541624Abstract: A method for fabricating a bipolar transistor includes forming collector, base, and emitter semiconductor layers on a substrate such that the layers form a vertical sequence with respect to an adjacent surface of the substrate. The method includes etching away a portion of a top one of the semiconductor layers to expose a portion of the base semiconductor layer and then, growing semiconductor on the exposed portion of the base layer. The top one of the semiconductor layers is the layer of the sequence that is located farthest from the substrate. The growing causes grown semiconductor to laterally surround a vertical portion of the top one of the semiconductor layers.Type: GrantFiled: July 21, 2003Date of Patent: June 2, 2009Assignee: Alcatel-Lucent USA Inc.Inventors: Young-Kai Chen, Rose Fasano Kopf, Wei-Jer Sung, Nils Guenter Weimann
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Publication number: 20090029536Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.Type: ApplicationFiled: September 29, 2008Publication date: January 29, 2009Inventors: Young-Kai Chen, Lay-Lay Chua, Vincent Etienne Houtsma, Rose Fasano Kopf, Andreas Leven, Chun-Ting Liu, Wei-Jer Sung, Yang Yang
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Patent number: 6911716Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.Type: GrantFiled: September 13, 2002Date of Patent: June 28, 2005Assignee: Lucent Technologies, Inc.Inventors: Young-Kai Chen, Lay-Lay Chua, Vincent Etienne Houtsma, Rose Fasano Kopf, Andreas Leven, Chun-Ting Liu, Wei-Jer Sung, Yang Yang
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Patent number: 6855613Abstract: A method of fabricating a III-V heterostructure semiconductor device. The method includes the steps of forming at least one conductive post overlying a semiconductor region to form a structure, encapsulating the structure and the conductive post to form a planarized cured passivation layer, and exposing the conductive post through the planarized cured passivation layer to form the semiconductor device.Type: GrantFiled: November 4, 1999Date of Patent: February 15, 2005Assignees: Lucent Technologies Inc., Agere Systems Inc.Inventors: Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate, Yu-Chi Wang
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Publication number: 20040046182Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.Type: ApplicationFiled: September 13, 2002Publication date: March 11, 2004Inventors: Young-Kai Chen, Lay-Lay Chua, Vincent Etienne Houtsma, Rose Fasano Kopf, Andreas Leven, Chun-Ting Liu, Wei-Jer Sung, Yang Yang
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Patent number: 6294018Abstract: The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO2 layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.Type: GrantFiled: September 15, 1999Date of Patent: September 25, 2001Assignee: Lucent TechnologiesInventors: Robert Alan Hamm, Rose Fasano Kopf, Christopher James Pinzone, Robert William Ryan, Alaric Tate
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Patent number: 6165859Abstract: The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd--Pt--Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.Type: GrantFiled: February 23, 1999Date of Patent: December 26, 2000Assignee: Lucent Technologies Inc.Inventors: Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate
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Patent number: 6156665Abstract: The specification describes a trilevel resist technique for defining metallization patterns by lift-off. The trilevel resist comprises two standard photoresist levels separated by a thin silicon oxide layer with approximate composition SiO.sub.2.Type: GrantFiled: April 13, 1998Date of Patent: December 5, 2000Assignee: Lucent Technologies Inc.Inventors: Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan
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Patent number: 6139995Abstract: The specification describes a photolithography process using multiple exposures to form z-dimension patterns. Multiple exposures at different thickness levels are made using photomasks aligned with a latent image of alignment marks formed during the first exposure. The latent image is visible to the alignment system of commercial steppers.Type: GrantFiled: March 10, 2000Date of Patent: October 31, 2000Assignee: Lucent Technologies Inc.Inventors: Jinwook Burm, Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate
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Patent number: 6042975Abstract: The specification describes a photolithography process using multiple exposures to form z-dimension patterns. Multiple exposures at different thickness levels are made using photomasks aligned with a latent image of alignment marks formed during the first exposure. The latent image is visible to the alignment system of commercial steppers.Type: GrantFiled: July 8, 1998Date of Patent: March 28, 2000Assignee: Lucent Technologies Inc.Inventors: Jinwook Burm, Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate
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Patent number: 5932379Abstract: The specification describes a technique for repairing wafer fractures that occur during wafer fabrication. The fractured pieces are joined edge-to-edge at the fracture line and bonded with epoxy adhesive. The method succeeds because the dimensions of the fracture line after bonding is within the reregistration tolerance of commercial step-and-repeat cameras and the reregistration capability of the camera allows normal exposure of sites that do not intersect the fracture line.Type: GrantFiled: February 24, 1998Date of Patent: August 3, 1999Assignee: Lucent Technologies Inc.Inventors: Jinwook Burm, Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate
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Patent number: 5907165Abstract: The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd-Pt-Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.Type: GrantFiled: May 1, 1998Date of Patent: May 25, 1999Assignee: Lucent Technologies Inc.Inventors: Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate