Patents by Inventor Ross Dermott

Ross Dermott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7683305
    Abstract: An imaging method and apparatus which use a pixel array for capturing images and for measuring ambient light conditions.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: March 23, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Johannes Solhusvik, Trygve Willassen, Ross Dermott, Michael Hartmann
  • Publication number: 20090084943
    Abstract: An imaging method and apparatus which use a pixel array for capturing images and for measuring ambient light conditions.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Inventors: Johannes Solhusvik, Trygve Willassen, Ross Dermott, Michael Hartmann
  • Patent number: 7276947
    Abstract: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Eric Becker, Tyler Gomm, Ross Dermott
  • Publication number: 20060274592
    Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.
    Type: Application
    Filed: August 17, 2006
    Publication date: December 7, 2006
    Inventors: Aaron Schoenfeld, Ross Dermott
  • Publication number: 20060261871
    Abstract: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.
    Type: Application
    Filed: July 26, 2006
    Publication date: November 23, 2006
    Inventors: Eric Becker, Tyler Gomm, Ross Dermott
  • Patent number: 7126393
    Abstract: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: October 24, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Eric Becker, Tyler Gomm, Ross Dermott
  • Publication number: 20060038597
    Abstract: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.
    Type: Application
    Filed: August 20, 2004
    Publication date: February 23, 2006
    Inventors: Eric Becker, Tyler Gomm, Ross Dermott
  • Publication number: 20050254327
    Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.
    Type: Application
    Filed: July 18, 2005
    Publication date: November 17, 2005
    Inventors: Aaron Schoenfeld, Ross Dermott
  • Publication number: 20050078539
    Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.
    Type: Application
    Filed: October 9, 2003
    Publication date: April 14, 2005
    Inventors: Aaron Schoenfeld, Ross Dermott