Abstract: A technique to identify a response cell in a ranging grant procedure is disclosed herein. The format of the response cell reduces the probability of erroneous response cell detection. The response cell is a conventional ATM cell whose payload includes multiple cell delineation bytes (CDBs).

Abstract: The present invention discloses a novel arbitration procedure for selecting among devices in a computer system requesting access to a single resource such as, for example, a system bus or main memory. The arbitration procedure provides an efficient means for guaranteeing the available system bus bandwidth to devices having high bandwidth requirements. Each device can be allotted a certain amount of bandwidth that is guaranteed to be available for that device within a given time interval. Excess bandwidth not consumed by the guaranteed allotments can be used as remainder (e.g., available but not guaranteed) bandwidth by the devices. The arbitration procedure further provides a guaranteed maximum latency so that no device is prevented from completing data transfers in a timely manner. The arbitration procedure still further provides the ability to dynamically program the amount of the bandwidth that is guaranteed a particular device.

Abstract: A synchronization backbone for use in a computer system having a system board containing at least one central processing unit for processing digital data, a memory coupled to the system board for storing the digital data, a plurality of subsystems, and a bus structure for transmitting electrical signals between the system board, the memory, and the plurality of subsystems. The synchronization backbone provides the infrastructure that enables professional quality synchronization between the various subsystems. A clock generator is used to generate a system clock that is transmitted to each of the subsystems. The sample rate of a designated subsystem is used as a digital synchronization signal. The selected digital synchronization signal is then transmitted to each of the other subsystems. A synchronization circuit adjusts the sample rates associated with the other subsystems according to the digital synchronization signal and the system clock.

Abstract: Disclosed is a three-dimensional display system that utilizes a host processor for performing geometric transformations and a local display processor for processing the user-supplied information which defines the object to be displayed. The display processor creates image data defining the location, color and intensity of each point of the overall image. This display processor processes and stores depth data which defines the corresponding depth relationships of the image points at each location of the overall image with the depth data being stored in a depth buffer, which is part of the display processor. The depth buffer is a two port memory device with one port being a random access port and the other being a serial access port. The display processor pieplines depth buffering operations by loading a row of data from the depth buffer into a shift register and then reading (a Read operation) the relevant pixel data through the serial access port which is connected to the shift register.

Abstract: The invention is a method and apparatus primarily for generating pixel representations for the video display of three-dimensional objects projected onto a two-dimensional pixel plane. The scanlines of the pixel plane are associated into N interlaced sets, each set having as members only scanlines having an equivalent vertical pixel location Modulo N. The image memory unit block utilizes both serial and parallel processing. For each color (red, green and blue) and for calculating depths, each image memory unit has a plurality N of Scanline Processors for generating the color or depth data to assign to a given pixel. Each of the Scanline Processors is associated with exactly one of the N sets of scanlines. The image memory units each also include a Master Controller. For certain objects, particularly triangular patches, the Master Controller sets up sequentially each Scanline Processor to render pixels on a specific scanline.