Abstract: A method of processing raw response signals for capacitive sense arrays is performed at an electronic device having one or more processors and a capacitive sense array. The process receives a raw response signal from the capacitive sense array. The process computes an offset signal that represents an average baseline value of the raw response signal over a period of time and filters the raw response signal to a limited frequency band, thereby forming a bandwidth limited signal. The process also computes a differential signal as the difference between the offset signal and the bandwidth limited signal and uses the differential signal to detect an object proximate to the capacitive sense array.

Abstract: Disclosed herein are systems, methods, and devices for power and energy metering. Devices may include first processing logic coupled to an isolator and configured to receive a first bit stream from a first modulator via the isolator. The first bit stream may be generated by the first modulator based on a first analog signal. The first processing logic may be further configured to receive a second bit stream from a second modulator via the isolator. The second bit stream may be generated by the second modulator based on a second analog signal. The processing logic may be further configured to generate a third bit stream based on a combination of the first bit stream with the second bit stream. The devices may also include second processing logic configured to generate an output signal based on one or more values of the third bit stream. The output signal may characterize a measurement of electrical power associated with an electrical circuit.

Abstract: Disclosed herein are systems, methods, and devices for power and energy metering. Devices may include first processing logic coupled to an isolator and configured to receive a first bit stream from a first modulator via the isolator. The first bit stream may be generated by the first modulator based on a first analog signal. The first processing logic may be further configured to receive a second bit stream from a second modulator via the isolator. The second bit stream may be generated by the second modulator based on a second analog signal. The processing logic may be further configured to generate a third bit stream based on a combination of the first bit stream with the second bit stream. The devices may also include second processing logic configured to generate an output signal based on one or more values of the third bit stream. The output signal may characterize a measurement of electrical power associated with an electrical circuit.

Abstract: A method of processing raw response signals for capacitive sense arrays is performed at an electronic device having one or more processors and a capacitive sense array. The process receives a raw response signal from the capacitive sense array. The process computes an offset signal that represents an average baseline value of the raw response signal over a period of time and filters the raw response signal to a limited frequency band, thereby forming a bandwidth limited signal. The process also computes a differential signal as the difference between the offset signal and the bandwidth limited signal and uses the differential signal to detect an object proximate to the capacitive sense array.

Abstract: A power factor correction circuit utilizes a digital controller string comprised of an analog-to-digital converter, which is input to a digital compensator followed by a pulse width modulation circuit for generating a switching pulse. The loop current in a regulator circuit such as a boost regulator is sensed and input to one side of a differential analog-to-digital converter, the other side thereof providing a digital reference current. This digital reference current is derived from comparing the input AC voltage to the regulator with the DC output voltage and processing these two voltages with a PFC algorithm to provide this reference voltage.

Abstract: A system for analyzing the operation of a switching power converter includes a digital controller for receiving an analog signal representing the output DC voltage of the power converter for comparison to a desired output voltage level and generating switching control signals to control the operation of the power supply to regulate the output DC voltage to said output voltage level. At least one portion of a control loop within the digital controller may be switched into the control loop in a first mode of operation and out of the control loop in a second mode of operation. A microcontroller emulates the operation of the at least one portion of the control loop during the second mode of operation.

Abstract: A system for controlling a soft start for a switching converter includes a digital feedback control system for receiving an analog voltage signal representing the output of a switching converter, for digitally processing the analog voltage signal by comparing it to a corrected reference voltage to generate a voltage error signal and for generating drive signals to control the operation of the switching converter to provide a regulated output. A microcontroller provides a secondary feedback loop for generating the corrected reference voltage. The secondary feedback loop enabling the output voltage signal to vary linearly over time during a soft start.