Abstract: A method of removing a metal includes exposing at least a portion of a metal-to-metal removal chemistry, wherein the metal removal chemistry comprises a chlorine-rich superoxidizer. In one embodiment, the metal being removed is a metal, such as a noble metal, that did not react with the semiconductor device during a salicidation process. In one embodiment, the chlorine-rich superoxidizer is formed by mixing hydrochloric acid in gas form with hydrogen peroxide and sulfuric acid. The metal can be exposed to the chlorine-rich superoxidizer in various ways, such as through an immersion or spray process.

Abstract: A semiconductor fabrication process includes forming a gate dielectric overlying a silicon substrate and forming a gate electrode overlying the gate dielectric. Source/drain recesses are then formed in the substrate on either side of the gate electrode using an NH4OH-based wet etch. A silicon-bearing semiconductor compound is then formed epitaxially to fill the source/drain recesses and thereby create source/drain structures. Exposed dielectric on the substrate upper surface may be removed using an HF dip prior to forming the source/drain recesses. Preferably, the NH4OH solution has an NH4OH concentration of less than approximately 0.5% and is maintained a temperature in the range of approximately 20 to 35° C. The silicon-bearing epitaxial compound may be silicon germanium for PMOS transistor or silicon carbide for NMOS transistors. A silicon dry etch process may be performed prior to the NH4OH wet etch to remove a surface portion of the source/drain regions.

Abstract: An insulating layer (24, 66, 82) is formed over a stack (14) of materials and a semiconductor substrate (12) and an implant is performed through the insulating layer into the semiconductor substrate. In one embodiment, spacers (26) are formed over the insulating layer (24), the insulating layer (24) is etched, and heavily doped regions (36) are formed adjacent the spacers. The spacers (26) are then removed and extension regions (50) and optional halo regions (46) are formed by implanting through the insulating layer (24). In one embodiment, the insulating layer (24) is in contact with the semiconductor substrate (12). In one embodiment, the stack (14) is a gate stack including a gate dielectric (18), a gate electrode (16), and an optional capping layer (22). The insulating layer (24, 66, 82) may include nitrogen, such as silicon nitride and aluminum nitride. In another embodiment, the insulating layer (24, 66, 82) may be hafnium oxide.